A low spur fractional-N frequency synthesizer architecture

Volodymyr Kratyuk; Pavan Kumar Hanumolu; Un Ku Moon; Kartikeya Mayaram

doi:10.1109/ISCAS.2005.1465210

A low spur fractional-N frequency synthesizer architecture

Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un Ku Moon, Kartikeya Mayaram

Research output: Contribution to journal › Conference article › peer-review

Abstract

A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loop filter with a discrete time comb filter which allows for the efficient suppression of fractional spurs. The proposed loop filter architecture can be efficiently implemented using switched capacitor techniques. The benefits of this approach are a low power frequency synthesizer design with low spur levels. An analysis of the fractional spurs in the fractional-N frequency synthesizers is also presented.

Original language	English (US)
Article number	1465210
Pages (from-to)	2807-2810
Number of pages	4
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
DOIs	https://doi.org/10.1109/ISCAS.2005.1465210
State	Published - 2005
Externally published	Yes
Event	IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan Duration: May 23 2005 → May 26 2005

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Electrical and Electronic Engineering

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10.1109/ISCAS.2005.1465210

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@article{231da809299847f1b1477acff0b73cee,

title = "A low spur fractional-N frequency synthesizer architecture",

abstract = "A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loop filter with a discrete time comb filter which allows for the efficient suppression of fractional spurs. The proposed loop filter architecture can be efficiently implemented using switched capacitor techniques. The benefits of this approach are a low power frequency synthesizer design with low spur levels. An analysis of the fractional spurs in the fractional-N frequency synthesizers is also presented.",

author = "Volodymyr Kratyuk and Hanumolu, {Pavan Kumar} and Moon, {Un Ku} and Kartikeya Mayaram",

year = "2005",

doi = "10.1109/ISCAS.2005.1465210",

language = "English (US)",

pages = "2807--2810",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 ; Conference date: 23-05-2005 Through 26-05-2005",

}

TY - JOUR

T1 - A low spur fractional-N frequency synthesizer architecture

AU - Kratyuk, Volodymyr

AU - Hanumolu, Pavan Kumar

AU - Moon, Un Ku

AU - Mayaram, Kartikeya

PY - 2005

Y1 - 2005

N2 - A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loop filter with a discrete time comb filter which allows for the efficient suppression of fractional spurs. The proposed loop filter architecture can be efficiently implemented using switched capacitor techniques. The benefits of this approach are a low power frequency synthesizer design with low spur levels. An analysis of the fractional spurs in the fractional-N frequency synthesizers is also presented.

AB - A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loop filter with a discrete time comb filter which allows for the efficient suppression of fractional spurs. The proposed loop filter architecture can be efficiently implemented using switched capacitor techniques. The benefits of this approach are a low power frequency synthesizer design with low spur levels. An analysis of the fractional spurs in the fractional-N frequency synthesizers is also presented.

UR - http://www.scopus.com/inward/record.url?scp=67649133144&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=67649133144&partnerID=8YFLogxK

U2 - 10.1109/ISCAS.2005.1465210

DO - 10.1109/ISCAS.2005.1465210

M3 - Conference article

AN - SCOPUS:67649133144

SN - 0271-4310

SP - 2807

EP - 2810

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

M1 - 1465210

T2 - IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005

Y2 - 23 May 2005 through 26 May 2005

ER -

A low spur fractional-N frequency synthesizer architecture

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