A low spur fractional-N frequency synthesizer architecture

Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un Ku Moon, Kartikeya Mayaram

Research output: Contribution to journalConference articlepeer-review

Abstract

A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loop filter with a discrete time comb filter which allows for the efficient suppression of fractional spurs. The proposed loop filter architecture can be efficiently implemented using switched capacitor techniques. The benefits of this approach are a low power frequency synthesizer design with low spur levels. An analysis of the fractional spurs in the fractional-N frequency synthesizers is also presented.

Original languageEnglish (US)
Article number1465210
Pages (from-to)2807-2810
Number of pages4
JournalProceedings - IEEE International Symposium on Circuits and Systems
DOIs
StatePublished - 2005
Externally publishedYes
EventIEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan
Duration: May 23 2005May 26 2005

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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