A Low-Power VLSI Architecture for Turbo Decoding

Computer Science

• Convolutional Code 100%
• Critical Path Delay 100%
• Data Processing 100%
• Experimental Result 100%
• Power Analysis 100%
• Processing Unit 100%
• Timing Analysis 100%
• Transistor 100%
• Very large-scale integration (VLSI) architecture 100%

Engineering

• Area Overhead 50%
• Convolutional Code 50%
• Critical Path 50%
• Data Block 50%
• Experimental Result 50%
• Modified atmosphere packaging 50%
• Processing Unit 50%
• Recursive 50%
• Transistor 50%
• Voltage Scaling 100%

Keyphrases

• Serially Concatenated Convolutional Codes 50%