A Low-Power VLSI Architecture for Turbo Decoding

Keyphrases

• Voltage Scaling 100%
• Block Interleaving 100%
• Turbo Decoding 100%
• VLSI Architecture 100%
• Low Power VLSI 100%
• Retiming 100%
• Interleaving Depth 100%
• Transistor Level 50%
• Timing Analysis 50%
• Power Analysis 50%
• Proposed Architecture 50%
• Power Saving 50%
• CMOS Process 50%
• Area Overhead 50%
• Critical Path Delay 50%
• Low Power Architecture 50%
• Add-compare-select 50%
• Data Processing Unit 50%
• MAP Decoder 50%
• Parallel Concatenated Convolutional Codes 50%

Engineering

• Voltage Scaling 100%
• Experimental Result 50%
• Data Block 50%
• Recursive 50%
• Area Overhead 50%
• Processing Unit 50%
• Critical Path 50%
• Convolutional Code 50%