@inproceedings{447b85283132443da729e454698a366d,
title = "A low-power VLSI architecture for turbo decoding",
abstract = "Presented in this paper is a low-power architecture for turbo decoding of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block-interleaved computation followed by folding, retiming and voltage scaling. Block-interleaved computation can be applied to any data processing unit that operates on data blocks and satisfies the following three properties: 1) computation between blocks are independent; 2) a block can be segmented into computationally independent sub-blocks; and 3) computation within a sub-block is recursive. The application of block-interleaved computation, folding and retiming reduces the critical path delay in the add-compare-select (ACS) kernel of MAP decoders by 50%-84% with an area overhead of 14%-70%. Subsequent application of voltage scaling results in up to 65% savings in power for a block-interleaving depth of 6. Experimental results obtained by transistor-level timing and power analysis tools demonstrate power savings of 20%-44% for a block-interleaving depth of 2 in a 0.25 μm CMOS process.",
keywords = "Added delay, Computer applications, Computer architecture, Concatenated codes, Convolutional codes, Data processing, Decoding, Kernel, Very large scale integration, Voltage",
author = "Lee, {Seok Jun} and Shanbhag, {N. R.} and Singer, {A. C.}",
note = "Publisher Copyright: {\textcopyright} 2003 ACM.; 2003 International Symposium on Low Power Electronics and Design, ISLPED 2003 ; Conference date: 25-08-2003 Through 27-08-2003",
year = "2003",
doi = "10.1109/LPE.2003.1231921",
language = "English (US)",
series = "Proceedings of the International Symposium on Low Power Electronics and Design",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "366--371",
booktitle = "ISLPED 2003 - Proceedings of the 2003 International Symposium on Low Power Electronics and Design",
address = "United States",
}