Abstract

Presented in this paper is a low-power architecture for turbo decoding of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block-interleaved computation followed by folding, retiming and voltage scaling. Block-interleaved computation can be applied to any data processing unit that operates on data blocks and satisfies the following three properties: 1) computation between blocks are independent; 2) a block can be segmented into computationally independent sub-blocks; and 3) computation within a sub-block is recursive. The application of block-interleaved computation, folding and retiming reduces the critical path delay in the add-compare-select (ACS) kernel of MAP decoders by 50%-84% with an area overhead of 14%-70%. Subsequent application of voltage scaling results in up to 65% savings in power for a block-interleaving depth of 6. Experimental results obtained by transistor-level timing and power analysis tools demonstrate power savings of 20%-44% for a block-interleaving depth of 2 in a 0.25 μm CMOS process.

Original languageEnglish (US)
Title of host publicationISLPED 2003 - Proceedings of the 2003 International Symposium on Low Power Electronics and Design
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages366-371
Number of pages6
ISBN (Electronic)158113682X
DOIs
StatePublished - 2003
Event2003 International Symposium on Low Power Electronics and Design, ISLPED 2003 - Seoul, Korea, Republic of
Duration: Aug 25 2003Aug 27 2003

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
Volume2003-January
ISSN (Print)1533-4678

Conference

Conference2003 International Symposium on Low Power Electronics and Design, ISLPED 2003
CountryKorea, Republic of
CitySeoul
Period8/25/038/27/03

Keywords

  • Added delay
  • Computer applications
  • Computer architecture
  • Concatenated codes
  • Convolutional codes
  • Data processing
  • Decoding
  • Kernel
  • Very large scale integration
  • Voltage

ASJC Scopus subject areas

  • Engineering(all)

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