Abstract

Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block-interleaved computation followed by folding, retiming and voltage scaling. Block-interleaved computation can be applied to any data processing unit that operates on data blocks and satisfies the following three properties: 1.) computation between blocks are independent, 2.) a block can be segmented into computationally independent sub-blocks, and 3.) computation within a sub-block is recursive. The application of block-interleaved computation, folding and retiming reduces the critical path delay in the add-compare-select (ACS) kernel of MAP decoders by 50% - 84% with an area overhead of 14% - 70%. Subsequent application of voltage scaling results in up to 65% savings in power for block-interleaving depth of 6. Experimental results obtained by transistor-level timing and power analysis tools demonstrate power savings of 20% - 44% for a block-interleaving depth of 2 in 0.25μm CMOS process.

Original languageEnglish (US)
Pages (from-to)366-371
Number of pages6
JournalProceedings of the International Symposium on Low Power Electronics and Design
StatePublished - Dec 1 2003
EventProceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03) - Seoul, Korea, Republic of
Duration: Aug 25 2003Aug 27 2003

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Decoding
Convolutional codes
Transistors
Voltage scaling

Keywords

  • Low power architecture
  • MAP decoder
  • Turbo decoding

ASJC Scopus subject areas

  • Engineering(all)

Cite this

@article{447b85283132443da729e454698a366d,
title = "A Low-Power VLSI Architecture for Turbo Decoding",
abstract = "Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block-interleaved computation followed by folding, retiming and voltage scaling. Block-interleaved computation can be applied to any data processing unit that operates on data blocks and satisfies the following three properties: 1.) computation between blocks are independent, 2.) a block can be segmented into computationally independent sub-blocks, and 3.) computation within a sub-block is recursive. The application of block-interleaved computation, folding and retiming reduces the critical path delay in the add-compare-select (ACS) kernel of MAP decoders by 50{\%} - 84{\%} with an area overhead of 14{\%} - 70{\%}. Subsequent application of voltage scaling results in up to 65{\%} savings in power for block-interleaving depth of 6. Experimental results obtained by transistor-level timing and power analysis tools demonstrate power savings of 20{\%} - 44{\%} for a block-interleaving depth of 2 in 0.25μm CMOS process.",
keywords = "Low power architecture, MAP decoder, Turbo decoding",
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AU - Shanbhag, Naresh R.

AU - Singer, Andrew C.

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N2 - Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block-interleaved computation followed by folding, retiming and voltage scaling. Block-interleaved computation can be applied to any data processing unit that operates on data blocks and satisfies the following three properties: 1.) computation between blocks are independent, 2.) a block can be segmented into computationally independent sub-blocks, and 3.) computation within a sub-block is recursive. The application of block-interleaved computation, folding and retiming reduces the critical path delay in the add-compare-select (ACS) kernel of MAP decoders by 50% - 84% with an area overhead of 14% - 70%. Subsequent application of voltage scaling results in up to 65% savings in power for block-interleaving depth of 6. Experimental results obtained by transistor-level timing and power analysis tools demonstrate power savings of 20% - 44% for a block-interleaving depth of 2 in 0.25μm CMOS process.

AB - Presented in this paper is a low-power architecture for turbo decodings of parallel concatenated convolutional codes. The proposed architecture is derived via the concept of block-interleaved computation followed by folding, retiming and voltage scaling. Block-interleaved computation can be applied to any data processing unit that operates on data blocks and satisfies the following three properties: 1.) computation between blocks are independent, 2.) a block can be segmented into computationally independent sub-blocks, and 3.) computation within a sub-block is recursive. The application of block-interleaved computation, folding and retiming reduces the critical path delay in the add-compare-select (ACS) kernel of MAP decoders by 50% - 84% with an area overhead of 14% - 70%. Subsequent application of voltage scaling results in up to 65% savings in power for block-interleaving depth of 6. Experimental results obtained by transistor-level timing and power analysis tools demonstrate power savings of 20% - 44% for a block-interleaving depth of 2 in 0.25μm CMOS process.

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