A low-power, reconfigurable adaptive equalizer architecture

J. Tschanz, N. R. Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents an architecture for an adaptive equalizer that is dynamically reconfigurable for low-power operation. The equalizer is composed of a signal processing block which accomplishes the filtering operations and a signal monitoring block which controls reconfiguration by monitoring the equalizer performance and dynamically powering up or down filter taps in order to conserve energy. This reconfigurable equalizer is used in the design of a 51.84 Mb/s VDSL receiver core, and simulation results are shown which demonstrate the power savings accomplished through reconfiguration.

Original languageEnglish (US)
Title of host publicationConference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers
EditorsMichael B. Matthews
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1391-1395
Number of pages5
ISBN (Electronic)0780357000, 9780780357006
DOIs
StatePublished - Jan 1 1999
Event33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999 - Pacific Grove, United States
Duration: Oct 24 1999Oct 27 1999

Publication series

NameConference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers
Volume2

Other

Other33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999
CountryUnited States
CityPacific Grove
Period10/24/9910/27/99

ASJC Scopus subject areas

  • Signal Processing
  • Computer Networks and Communications

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