@inproceedings{408a0f3ae843421287dee0c5f336fa54,
title = "A low-power, reconfigurable adaptive equalizer architecture",
abstract = "This paper presents an architecture for an adaptive equalizer that is dynamically reconfigurable for low-power operation. The equalizer is composed of a signal processing block which accomplishes the filtering operations and a signal monitoring block which controls reconfiguration by monitoring the equalizer performance and dynamically powering up or down filter taps in order to conserve energy. This reconfigurable equalizer is used in the design of a 51.84 Mb/s VDSL receiver core, and simulation results are shown which demonstrate the power savings accomplished through reconfiguration.",
author = "J. Tschanz and Shanbhag, {N. R.}",
note = "Publisher Copyright: {\textcopyright} 1999 IEEE.; 33rd Asilomar Conference on Signals, Systems, and Computers, ACSSC 1999 ; Conference date: 24-10-1999 Through 27-10-1999",
year = "1999",
doi = "10.1109/ACSSC.1999.831934",
language = "English (US)",
series = "Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1391--1395",
editor = "Matthews, {Michael B.}",
booktitle = "Conference Record of the 33rd Asilomar Conference on Signals, Systems, and Computers",
address = "United States",
}