A low power pipelined ADC using capacitor and opamp sharing technique with a scheme to cancel the effect of signal dependent kickback

Naga Sasidhar, Youn Jae Kook, Seiji Takeuchi, Koichi Hamashita, Kaoru Takasuka, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Contribution to journalArticlepeer-review

Abstract

A new capacitor and opamp sharing technique that enables a very efficient low-power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back or memory effect in capacitors in the absence of a sample and hold is also presented. Fabricated in a 0.18 μ m CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm2 of active die area and achieves 66.7 dB SFDR and 53.2 dB SNDR when a 1 MHz input signal is digitized at 80 MS/s. The SFDR and SNDR are unchanged for a 50 MHz input signal. The prototype ADC consumes 36 mW at 1.8 V supply, of which the analog portion consumes 24 mW.

Original languageEnglish (US)
Article number5226688
Pages (from-to)2392-2401
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume44
Issue number9
DOIs
StatePublished - Sep 2009
Externally publishedYes

Keywords

  • Analog-to-digital converter (ADC)
  • Capacitor and opamp sharing
  • Data converter
  • High speed
  • Kickback
  • Low power
  • Memory effect
  • Pipeline

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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