TY - JOUR
T1 - A low power pipelined ADC using capacitor and opamp sharing technique with a scheme to cancel the effect of signal dependent kickback
AU - Sasidhar, Naga
AU - Kook, Youn Jae
AU - Takeuchi, Seiji
AU - Hamashita, Koichi
AU - Takasuka, Kaoru
AU - Hanumolu, Pavan Kumar
AU - Moon, Un Ku
N1 - Funding Information:
Manuscript received November 26, 2008; revised April 27, 2009. Current version published August 26, 2009. This work was supported by Asahi Kasei Microdevices Corporation. N. Sasidhar was with Oregon State University, Corvallis, OR 97331 USA, and is now with Intel Corporation, Hillsboro, OR 97124 USA (e-mail: [email protected]). Y. Kook is with Analog Devices, Wilmington, MA 01887 USA. S. Takeuchi, K. Hamashita, and K. Takasuka are with Asahi Kasei Microde-vices, Atsugi, Kanagawa 243-0021, Japan. P. K. Hanumolu and U. Moon are with the School of Electrical Engineering and Computer Science, Oregon State University, Corvallis, OR 97331 USA. Digital Object Identifier 10.1109/JSSC.2009.2025408
PY - 2009/9
Y1 - 2009/9
N2 - A new capacitor and opamp sharing technique that enables a very efficient low-power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back or memory effect in capacitors in the absence of a sample and hold is also presented. Fabricated in a 0.18 μ m CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm2 of active die area and achieves 66.7 dB SFDR and 53.2 dB SNDR when a 1 MHz input signal is digitized at 80 MS/s. The SFDR and SNDR are unchanged for a 50 MHz input signal. The prototype ADC consumes 36 mW at 1.8 V supply, of which the analog portion consumes 24 mW.
AB - A new capacitor and opamp sharing technique that enables a very efficient low-power pipeline ADC design is proposed. A new method to cancel the effect of signal-dependent kick-back or memory effect in capacitors in the absence of a sample and hold is also presented. Fabricated in a 0.18 μ m CMOS process, the prototype 11-bit pipelined ADC occupies 2.2 mm2 of active die area and achieves 66.7 dB SFDR and 53.2 dB SNDR when a 1 MHz input signal is digitized at 80 MS/s. The SFDR and SNDR are unchanged for a 50 MHz input signal. The prototype ADC consumes 36 mW at 1.8 V supply, of which the analog portion consumes 24 mW.
KW - Analog-to-digital converter (ADC)
KW - Capacitor and opamp sharing
KW - Data converter
KW - High speed
KW - Kickback
KW - Low power
KW - Memory effect
KW - Pipeline
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U2 - 10.1109/JSSC.2009.2025408
DO - 10.1109/JSSC.2009.2025408
M3 - Article
AN - SCOPUS:70249132251
SN - 0018-9200
VL - 44
SP - 2392
EP - 2401
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 9
M1 - 5226688
ER -