A low-power digital filter IC via soft DSP

R. Hegde, N. R. Shanbhag

Research output: Contribution to journalConference articlepeer-review


In this paper we present an integrated circuit implementation of a soft DSP based low-power digital filter in 0.35μm, 3.3V CMOS process. Soft DSP is a low-power technique that employs voltage overscaling (VOS) and algorithmic noise-tolerance (ANT) to push the limits of energy-efficiency beyond that achievable by voltage scaling along. VOS refers to scaling the supply voltage beyond the limit imposed by the throughput constraints. ANT is an algorithmic level error-control technique that is employed to restore the algorithmic performance degradation in terms of output signal-to-noise ratio (SNR) caused by VOS. Measured results indicate 40% - 67% reduction in energy dissipation over optimally voltage-scaled systems with less than 1db loss in S N R for a wide range of filter bandwidths (0.05fs - 0.25fs, where fs is the sampling frequency).

Original languageEnglish (US)
Pages (from-to)309-312
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
StatePublished - 2001
Externally publishedYes
EventIEEE 2001 Custom Integrated Circuits Conference - San Diego, CA, United States
Duration: May 6 2001May 9 2001

ASJC Scopus subject areas

  • Electrical and Electronic Engineering


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