A Low-Noise Frequency Synthesizer Using Multiphase Generation and Combining Techniques

A ring oscillator (RO)-based low-noise frequency synthesizer is presented. Phase noise degradation caused by jitter accumulation in conventional RO-based synthesizers is alleviated by increasing the update rate. To this end, multiple phases of the crystal oscillator (XO) output are generated and edge combined to produce a clock at an integer multiple of the XO frequency, which is then used as a reference clock to a conventional injection-locked clock multiplier that generates a low-noise high-frequency output clock. Unlike conventional delay-locked loop-based multiphase generators (MPGs), the proposed MPG is implemented by using a simple $RC$ network connected between the XO terminals. As a result, the proposed approach consumes little power and, more importantly, does not suffer from jitter accumulation. Inevitable phase-spacing errors caused by process, voltage, and temperature variations, and component mismatches are mitigated by using digital background calibration. Fabricated in a 65-nm CMOS process, the prototype synthesizer operates with a standard 54-MHz crystal and generates a 432-MHz clock by combining eight phases generated by the proposed MPG. Using 432-MHz clock as the reference, an injection-locked clock multiplier generates a 5-GHz output with a measured integrated output jitter of 245 fs_rms. The total power consumption is 8.2 mW of which the XO frequency multiplier consumes only 2.8 mW.