A Highly Reconfigurable Bit-Level Duty-Cycled TRF Receiver Achieving -106-dBm Sensitivity and 33-nW Average Power Consumption

Jesse Moody, Songbin Gong, Benton H. Calhoun, Steven M. Bowers, Anjana Dissanayake, Henry Bishop, Ruochen Lu, Ningxi Liu, Divya Duvvuri, Anming Gao, Daniel Truesdell, N. Scott Barker

Research output: Contribution to journalArticlepeer-review

Abstract

This letter presents a reconfigurable wake-up receiver, which obtains -106-dBm sensitivity with power consumption as low as 33 nW. Bit-level duty cycling provides 68-dB RF gain at sub- \mu \text{W} average power consumption, improving sensitivity over other sub- \mu \text{W} receivers. The receiver rejects interference using a compact RF MEMS filter and a fully automatic gain and offset control loop. Digital tuning of dc power, latency, and sensitivity provides high levels of flexibility to enable a wide variety of applications, spanning latency from 240 ms to 5 s, dc power consumption from 288 nW to 33 nW, and sensitivity from -106 dBm to -103 dBm. Three example modes are presented to highlight the range of this tuning.

Original languageEnglish (US)
Article number8915724
Pages (from-to)309-312
Number of pages4
JournalIEEE Solid-State Circuits Letters
Volume2
Issue number12
DOIs
StatePublished - Dec 2019

Keywords

  • Low power wide area network (LPWAN)
  • ultra low-power radio
  • wake-up radio
  • wireless sensing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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