Ever-growing demand for higher communication bandwidth in high performance compute systems is driving the need for energy-efficient multi-Gb/s I/O serial links. Improved power efficiency was demonstrated using adaptive supply regulation [1, 2]. However, power losses in the DC-DC converter needed to generate the optimal supply voltage and the difficulty in operating analog circuits at low voltages limit the power savings. Instead of scaling the supply with the data rate, we seek to operate with two fixed voltages and eliminate the need for a high-efficiency DC-DC converter. To this end, this paper presents a serial link using a highly efficient current recycling-based implicit DC-DC conversion to generate 0.6V from a 1.2V supply. Highly digital clocking circuits capable of operating at 0.6V maximize power savings. A 0.5-to-4Gb/s serial-link transceiver is designed in a 1.2V LP 90nm CMOS process to operate with a short channel and ple-siochronous timing. The transceiver dissipates 1.9mW/Gb/s at 3.2Gb/s.