TY - GEN
T1 - A highly digital 0.5-to-4Gb/s 1.9mW/Gb/s serial-link transceiver using current-recycling in 90nm CMOS
AU - Inti, Rajesh
AU - Elshazly, Amr
AU - Young, Brian
AU - Yin, Wenjing
AU - Kossel, Marcel
AU - Toifl, Thomas
AU - Hanumolu, Pavan Kumar
PY - 2011
Y1 - 2011
N2 - Ever-growing demand for higher communication bandwidth in high performance compute systems is driving the need for energy-efficient multi-Gb/s I/O serial links. Improved power efficiency was demonstrated using adaptive supply regulation [1, 2]. However, power losses in the DC-DC converter needed to generate the optimal supply voltage and the difficulty in operating analog circuits at low voltages limit the power savings. Instead of scaling the supply with the data rate, we seek to operate with two fixed voltages and eliminate the need for a high-efficiency DC-DC converter. To this end, this paper presents a serial link using a highly efficient current recycling-based implicit DC-DC conversion to generate 0.6V from a 1.2V supply. Highly digital clocking circuits capable of operating at 0.6V maximize power savings. A 0.5-to-4Gb/s serial-link transceiver is designed in a 1.2V LP 90nm CMOS process to operate with a short channel and ple-siochronous timing. The transceiver dissipates 1.9mW/Gb/s at 3.2Gb/s.
AB - Ever-growing demand for higher communication bandwidth in high performance compute systems is driving the need for energy-efficient multi-Gb/s I/O serial links. Improved power efficiency was demonstrated using adaptive supply regulation [1, 2]. However, power losses in the DC-DC converter needed to generate the optimal supply voltage and the difficulty in operating analog circuits at low voltages limit the power savings. Instead of scaling the supply with the data rate, we seek to operate with two fixed voltages and eliminate the need for a high-efficiency DC-DC converter. To this end, this paper presents a serial link using a highly efficient current recycling-based implicit DC-DC conversion to generate 0.6V from a 1.2V supply. Highly digital clocking circuits capable of operating at 0.6V maximize power savings. A 0.5-to-4Gb/s serial-link transceiver is designed in a 1.2V LP 90nm CMOS process to operate with a short channel and ple-siochronous timing. The transceiver dissipates 1.9mW/Gb/s at 3.2Gb/s.
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U2 - 10.1109/ISSCC.2011.5746260
DO - 10.1109/ISSCC.2011.5746260
M3 - Conference contribution
AN - SCOPUS:79955728572
SN - 9781612843001
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 152
EP - 153
BT - 2011 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2011
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011
Y2 - 20 February 2011 through 24 February 2011
ER -