TY - GEN
T1 - A highly compressed timing macro-modeling algorithm for hierarchical and incremental timing analysis
AU - Lai, Tin Yin
AU - Wong, Martin D.F.
N1 - Funding Information:
This work is sponsored by the National Science Foundation under Grant CFF-1421563 and CFF-171883. The authors acknowledge the TAU 2017 Timing Contest committees for the discussion, and team iTimerM 2.0.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/2/20
Y1 - 2018/2/20
N2 - Large-scale hierarchical and incremental timing analysis has driven the need for highly compressed timing macro-models. A small timing macro-model for accelerating hierarchical timing is desired because the size of incremental changes dramatically increases as the macro-models are widely used in the large design process. In fact, it takes days for an incremental timing analysis on millions of gates with thousands of incremental changes. To date, the timing macro-models generated by timing macro-modeling algorithms from all the previous works are not compact enough. In this work, we provide four essential techniques in our timing macro-modeling algorithm, which are able to generate highly compressed timing macro-models for hierarchical and incremental timing analysis. In addition, our timing macro-model maintain high accuracy and the efficiency in generating our macro-models. Our algorithm generates timing macro-models where the model sizes are 9% better in the number of nodes and 19% better in the number of edges than the original circuit. Our work outperforms the state of arts significantly in both model size and the runtime in macro-model usage.
AB - Large-scale hierarchical and incremental timing analysis has driven the need for highly compressed timing macro-models. A small timing macro-model for accelerating hierarchical timing is desired because the size of incremental changes dramatically increases as the macro-models are widely used in the large design process. In fact, it takes days for an incremental timing analysis on millions of gates with thousands of incremental changes. To date, the timing macro-models generated by timing macro-modeling algorithms from all the previous works are not compact enough. In this work, we provide four essential techniques in our timing macro-modeling algorithm, which are able to generate highly compressed timing macro-models for hierarchical and incremental timing analysis. In addition, our timing macro-model maintain high accuracy and the efficiency in generating our macro-models. Our algorithm generates timing macro-models where the model sizes are 9% better in the number of nodes and 19% better in the number of edges than the original circuit. Our work outperforms the state of arts significantly in both model size and the runtime in macro-model usage.
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U2 - 10.1109/ASPDAC.2018.8297300
DO - 10.1109/ASPDAC.2018.8297300
M3 - Conference contribution
AN - SCOPUS:85045328741
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 166
EP - 171
BT - ASP-DAC 2018 - 23rd Asia and South Pacific Design Automation Conference, Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018
Y2 - 22 January 2018 through 25 January 2018
ER -