A high-throughput VLSI architecture for linear turbo equalization

Seok Jun Lee, Naresh R Shanbhag

Research output: Contribution to journalArticlepeer-review


Turbo equalization dramatically improves bit error rate (BER) over separate equalization and decoding receivers. However, turbo equalization has low throughput due to iterative processing where a soft-input soft-output (SISO) equalizer or decoder cannot begin before the end of the previous SISO decoding iteration. In this paper, we propose a high-throughput VLSI architecture for linear turbo equalizers via re-scheduling the soft information updates on a factor graph. The proposed method enables SISO equalizers and decoders to run concurrently thereby reducing the processing time. Thus, the proposed architecture increases throughput by 40%-75% without any loss in BER.

Original languageEnglish (US)
Pages (from-to)2142-2146
Number of pages5
JournalConference Record of the Asilomar Conference on Signals, Systems and Computers
StatePublished - 2003

ASJC Scopus subject areas

  • Signal Processing
  • Computer Networks and Communications


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