@inproceedings{e91968abdf4e4f5191b76a274ef682aa,
title = "A high-speed architecture for ADPCM codec",
abstract = "A pipelined architecture for adaptive pulse code modulation (ADPCM) is presented. The architecture is developed by the application of relaxed form of look-ahead. The hardware overhead is only the the pipelining latches and is independent of the number of quantizer levels, the predictor order and the pipelining level. The codec latency is smaller than the level of pipelining. Under the assumption of small quantization error, the convergence properties of the pipelined architecture are compared with that of the serial one. Speech and image coding examples are presented to support the conclusions in this paper.",
author = "Shanbhag, {Naresh R.} and Parhi, {Keshab K.}",
note = "Publisher Copyright: {\textcopyright} 1992 IEEE. Copyright: Copyright 2019 Elsevier B.V., All rights reserved.; 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 ; Conference date: 10-05-1992 Through 13-05-1992",
year = "1992",
doi = "10.1109/ISCAS.1992.230216",
language = "English (US)",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1499--1502",
booktitle = "1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992",
address = "United States",
}