A high-rate, low-power, ASIC speech decoder using finite state transducers

Jeffrey R. Johnston, Robin A Rutenbar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The use of Finite State Transducers in speech recognition has been increasing in recent years. Their application in speech decoding allows for a tradeoff between larger memory requirements and less run-time computation. We believe that this paradigm is especially well suited for a highspeed, energy-efficient hardware solution where customized caching, reduced bit widths, and prefetching can be used to mitigate the effect of the increased model size. We present a virtual silicon prototype for a novel hardware architecture that, using these optimizations and running at 556MHz, is capable of performing recognition on the Wall Street Journal 60K- word speech model with 92.3 percent accuracy a speed 127 times faster than real time, while consuming less than 0.5 watts.

Original languageEnglish (US)
Title of host publicationProceedings - 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012
Pages77-85
Number of pages9
DOIs
StatePublished - Dec 13 2012
Event2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012 - Delft, Netherlands
Duration: Jul 9 2012Jul 11 2012

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
ISSN (Print)1063-6862

Other

Other2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2012
CountryNetherlands
CityDelft
Period7/9/127/11/12

Keywords

  • ASIC
  • finite state transducer
  • hardware
  • speech recognition

ASJC Scopus subject areas

  • Hardware and Architecture
  • Computer Networks and Communications

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