A high-PSR LDO using a feedforward supply-noise cancellation technique

Bangda Yang; Brian Drost; Sachin Rao; Pavan Kumar Hanumolu

doi:10.1109/CICC.2011.6055409

A high-PSR LDO using a feedforward supply-noise cancellation technique

Bangda Yang, Brian Drost, Sachin Rao, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A feed-forward noise cancellation (FFNC) technique to improve the power supply noise rejection (PSR) of a low dropout regulator (LDO) is presented. The proposed FFNC operates in conjunction with a conventional LDO and extends the noise rejection bandwidth by nearly an order of magnitude. Fabricated in 0.18μm CMOS, at 10mA load current, the prototype achieves a PSR of -50dB and -25dB at 1MHz and 10MHz supply noise frequencies, respectively. Compared to a conventional LDO, this represents an improvement of at least 30dB at 1MHz and 15dB at 10MHz. The prototype uses only 20pF load capacitance and occupies an active area of 0.04mm².

Original language	English (US)
Title of host publication	2011 IEEE Custom Integrated Circuits Conference, CICC 2011
DOIs	https://doi.org/10.1109/CICC.2011.6055409
State	Published - 2011
Externally published	Yes
Event	33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011 - San Jose, CA, United States Duration: Sep 19 2011 → Sep 21 2011

Other

Other	33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011
Country/Territory	United States
City	San Jose, CA
Period	9/19/11 → 9/21/11

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/CICC.2011.6055409

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Yang, B, Drost, B, Rao, S & Hanumolu, PK 2011, A high-PSR LDO using a feedforward supply-noise cancellation technique. in 2011 IEEE Custom Integrated Circuits Conference, CICC 2011., 6055409, 33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011, San Jose, CA, United States, 9/19/11. https://doi.org/10.1109/CICC.2011.6055409

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abstract = "A feed-forward noise cancellation (FFNC) technique to improve the power supply noise rejection (PSR) of a low dropout regulator (LDO) is presented. The proposed FFNC operates in conjunction with a conventional LDO and extends the noise rejection bandwidth by nearly an order of magnitude. Fabricated in 0.18μm CMOS, at 10mA load current, the prototype achieves a PSR of -50dB and -25dB at 1MHz and 10MHz supply noise frequencies, respectively. Compared to a conventional LDO, this represents an improvement of at least 30dB at 1MHz and 15dB at 10MHz. The prototype uses only 20pF load capacitance and occupies an active area of 0.04mm2.",

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year = "2011",

doi = "10.1109/CICC.2011.6055409",

language = "English (US)",

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N2 - A feed-forward noise cancellation (FFNC) technique to improve the power supply noise rejection (PSR) of a low dropout regulator (LDO) is presented. The proposed FFNC operates in conjunction with a conventional LDO and extends the noise rejection bandwidth by nearly an order of magnitude. Fabricated in 0.18μm CMOS, at 10mA load current, the prototype achieves a PSR of -50dB and -25dB at 1MHz and 10MHz supply noise frequencies, respectively. Compared to a conventional LDO, this represents an improvement of at least 30dB at 1MHz and 15dB at 10MHz. The prototype uses only 20pF load capacitance and occupies an active area of 0.04mm2.

AB - A feed-forward noise cancellation (FFNC) technique to improve the power supply noise rejection (PSR) of a low dropout regulator (LDO) is presented. The proposed FFNC operates in conjunction with a conventional LDO and extends the noise rejection bandwidth by nearly an order of magnitude. Fabricated in 0.18μm CMOS, at 10mA load current, the prototype achieves a PSR of -50dB and -25dB at 1MHz and 10MHz supply noise frequencies, respectively. Compared to a conventional LDO, this represents an improvement of at least 30dB at 1MHz and 15dB at 10MHz. The prototype uses only 20pF load capacitance and occupies an active area of 0.04mm2.

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A high-PSR LDO using a feedforward supply-noise cancellation technique

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