A high-efficiency, high-power-density buffer architecture is proposed for power pulsation decoupling in power conversion between dc and single-phase ac. We present an active decoupling solution that yields improved efficiency and reduced circuit complexity compared to existing solutions. In the proposed architecture, the main energy storage capacitor is connected in series with an active buffer converter across the dc bus. The series-stacked capacitor blocks the majority of the dc bus voltage to reduce the voltage stress on the buffer converter, such that fast, low-voltage transistors can be employed for the buffer converter. Moreover, the series capacitor provides the majority of the power pulsation decoupling through a wide voltage swing, and the buffer converter only needs to process a small fraction of the total power of the entire architecture, allowing a very small active circuit volume and very high system efficiency. The circuit operation and design constraints are analyzed in detail. In the proposed buffer architecture, the series stacking of a nearly lossless capacitor and a lossy converter presents a challenge of capacitor voltage balancing and power loss compensation. We propose a control scheme exploiting the small ripple in the bus voltage and dc input current to compensate for the power loss in the buffer converter while maintaining the voltage balance. Light-load techniques are also introduced to ensure that the buffer architecture meets strict ripple requirements while providing sufficient loss compensation. A 2-kW hardware prototype based on low-voltage GaN switches has been built to demonstrate the performance of the proposed solution. A power density of 25 W/cm3 (410 W/in3) by rectangular box volume and an efficiency above 98.9% across a wide load range has been experimentally verified.
- Active filters, circuit topology, digital control, DC-AC power converters, power smoothing
ASJC Scopus subject areas
- Electrical and Electronic Engineering