A gate-level simulation environment for alpha-particle-induced transient faults

Hungse Cha, Elizabeth M. Rudnick, Janak H. Patel, Ravishankar K. Iyer, Gwan S. Choi

Research output: Contribution to journalArticlepeer-review

Abstract

Mixed analog and digital mode simulators have been available for accurate α-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. Although the environment was developed for α-particle-induced transient faults, the methodology can be used for any transient fault which can be modeled as a transient pulse of some width. The simulation environment uses a gate level timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses logic level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The environment is demonstrated on a set of ISCAS-89 sequential benchmark circuits.

Original languageEnglish (US)
Pages (from-to)1248-1256
Number of pages9
JournalIEEE Transactions on Computers
Volume45
Issue number11
DOIs
StatePublished - Dec 1 1996

Keywords

  • Fault-tolerance
  • Single event upset
  • Transient fault injection
  • Transient fault modeling
  • Transient fault simulation

ASJC Scopus subject areas

  • Software
  • Theoretical Computer Science
  • Hardware and Architecture
  • Computational Theory and Mathematics

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