TY - GEN
T1 - A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering
AU - Choi, Woo Seok
AU - Anand, Tejasvi
AU - Shu, Guanghua
AU - Hanumolu, Pavan Kumar
PY - 2013
Y1 - 2013
N2 - A digital burst-mode CDR employs feed-forward data edge injection and a digital feedback loop to achieve instantaneous phase locking, data-rate tracking, and input jitter filtering. Fabricated in a 90nm CMOS process, the prototype receiver achieves instantaneous locking on the very first data edge and consumes 6.1mW at 2.2Gb/s. By controlling the edge injection rate, the proposed architecture allows variable JTRAN bandwidth from 5MHz to 40MHz.
AB - A digital burst-mode CDR employs feed-forward data edge injection and a digital feedback loop to achieve instantaneous phase locking, data-rate tracking, and input jitter filtering. Fabricated in a 90nm CMOS process, the prototype receiver achieves instantaneous locking on the very first data edge and consumes 6.1mW at 2.2Gb/s. By controlling the edge injection rate, the proposed architecture allows variable JTRAN bandwidth from 5MHz to 40MHz.
UR - http://www.scopus.com/inward/record.url?scp=84883746803&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84883746803&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84883746803
SN - 9784863483484
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - C280-C281
BT - 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
T2 - 2013 Symposium on VLSI Circuits, VLSIC 2013
Y2 - 12 June 2013 through 14 June 2013
ER -