A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering

Woo Seok Choi, Tejasvi Anand, Guanghua Shu, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A digital burst-mode CDR employs feed-forward data edge injection and a digital feedback loop to achieve instantaneous phase locking, data-rate tracking, and input jitter filtering. Fabricated in a 90nm CMOS process, the prototype receiver achieves instantaneous locking on the very first data edge and consumes 6.1mW at 2.2Gb/s. By controlling the edge injection rate, the proposed architecture allows variable JTRAN bandwidth from 5MHz to 40MHz.

Original languageEnglish (US)
Title of host publication2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
PagesC280-C281
StatePublished - Sep 17 2013
Externally publishedYes
Event2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan
Duration: Jun 12 2013Jun 14 2013

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2013 Symposium on VLSI Circuits, VLSIC 2013
CountryJapan
CityKyoto
Period6/12/136/14/13

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Choi, W. S., Anand, T., Shu, G., & Hanumolu, P. K. (2013). A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers (pp. C280-C281). [6578695] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).