A fast and accurate delay estimation method for buffered interconnects

Youxin Gao, D. F. Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present a fast and accurate delay estimation method for buffered interconnects. The interconnect wire is modeled by the transmission line model which is more accurate and efficient than lumped circuit model. For the interconnect wire, we specify the wire shape to be of the form f(x)=ae-bx. Note that if we let b=0, our work is reduced to uniform wire case. By using the first three poles in the transfer function, we derive analytical expressions for calculating delay at any threshold voltage under a finite ramp input. The expressions involved in calculating coefficients in the transfer function are also analytical. We use k-factor equations to estimate delays for buffers. Since the k-factor equations require a loading capacitance for delay computation, we use the effective capacitance technique to calculate the effective capacitance for each interconnect wire which is connected to a buffer. Therefore, our delay calculation for buffered interconnects is analytical and thus very efficient. Our experiments show that signal waveforms estimated by our method are very close to SPICE's results.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP-DAC 2001
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages533-538
Number of pages6
ISBN (Electronic)0780366336
DOIs
StatePublished - Jan 1 2001
Externally publishedYes
EventAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan
Duration: Jan 30 2001Feb 2 2001

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2001-January

Other

OtherAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
CountryJapan
CityYokohama
Period1/30/012/2/01

Keywords

  • Capacitance
  • Delay effects
  • Delay estimation
  • Distributed parameter circuits
  • Equations
  • Integrated circuit interconnections
  • Shape
  • Threshold voltage
  • Transfer functions
  • Wire

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

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  • Cite this

    Gao, Y., & Wong, D. F. (2001). A fast and accurate delay estimation method for buffered interconnects. In Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001 (pp. 533-538). [913363] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2001-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2001.913363