A fast and accurate delay estimation method for buffered interconnects

Youxin Gao, Martin D F Wong

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present a fast and accurate delay estimation method for buffered interconnects. The interconnect wire is modeled by the transmission line model which is more accurate and efficient than lumped circuit model. For the interconnect wire, we specify the wire shape to be of the form f(x)=ae-bx. Note that if we let b=0, our work is reduced to uniform wire case. By using the first three poles in the transfer function, we derive analytical expressions for calculating delay at any threshold voltage under a finite ramp input. The expressions involved in calculating coefficients in the transfer function are also analytical. We use k-factor equations to estimate delays for buffers. Since the k-factor equations require a loading capacitance for delay computation, we use the effective capacitance technique to calculate the effective capacitance for each interconnect wire which is connected to a buffer. Therefore, our delay calculation for buffered interconnects is analytical and thus very efficient. Our experiments show that signal waveforms estimated by our method are very close to SPICE's results.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP-DAC 2001
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2001
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages533-538
Number of pages6
ISBN (Electronic)0780366336
DOIs
StatePublished - Jan 1 2001
Externally publishedYes
EventAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001 - Yokohama, Japan
Duration: Jan 30 2001Feb 2 2001

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume2001-January

Other

OtherAsia and South Pacific Design Automation Conference 2001, ASP-DAC 2001
CountryJapan
CityYokohama
Period1/30/012/2/01

Fingerprint

Wire
Capacitance
Transfer functions
SPICE
Threshold voltage
Poles
Electric lines
Networks (circuits)
Experiments

Keywords

  • Capacitance
  • Delay effects
  • Delay estimation
  • Distributed parameter circuits
  • Equations
  • Integrated circuit interconnections
  • Shape
  • Threshold voltage
  • Transfer functions
  • Wire

ASJC Scopus subject areas

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Cite this

Gao, Y., & Wong, M. D. F. (2001). A fast and accurate delay estimation method for buffered interconnects. In Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001 (pp. 533-538). [913363] (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2001-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.2001.913363

A fast and accurate delay estimation method for buffered interconnects. / Gao, Youxin; Wong, Martin D F.

Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., 2001. p. 533-538 913363 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 2001-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Gao, Y & Wong, MDF 2001, A fast and accurate delay estimation method for buffered interconnects. in Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001., 913363, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 2001-January, Institute of Electrical and Electronics Engineers Inc., pp. 533-538, Asia and South Pacific Design Automation Conference 2001, ASP-DAC 2001, Yokohama, Japan, 1/30/01. https://doi.org/10.1109/ASPDAC.2001.913363
Gao Y, Wong MDF. A fast and accurate delay estimation method for buffered interconnects. In Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc. 2001. p. 533-538. 913363. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). https://doi.org/10.1109/ASPDAC.2001.913363
Gao, Youxin ; Wong, Martin D F. / A fast and accurate delay estimation method for buffered interconnects. Proceedings of the ASP-DAC 2001: Asia and South Pacific Design Automation Conference 2001. Institute of Electrical and Electronics Engineers Inc., 2001. pp. 533-538 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC).
@inproceedings{4827a3a3ec724ef0aa5e4c7d3bf7addf,
title = "A fast and accurate delay estimation method for buffered interconnects",
abstract = "In this paper, we present a fast and accurate delay estimation method for buffered interconnects. The interconnect wire is modeled by the transmission line model which is more accurate and efficient than lumped circuit model. For the interconnect wire, we specify the wire shape to be of the form f(x)=ae-bx. Note that if we let b=0, our work is reduced to uniform wire case. By using the first three poles in the transfer function, we derive analytical expressions for calculating delay at any threshold voltage under a finite ramp input. The expressions involved in calculating coefficients in the transfer function are also analytical. We use k-factor equations to estimate delays for buffers. Since the k-factor equations require a loading capacitance for delay computation, we use the effective capacitance technique to calculate the effective capacitance for each interconnect wire which is connected to a buffer. Therefore, our delay calculation for buffered interconnects is analytical and thus very efficient. Our experiments show that signal waveforms estimated by our method are very close to SPICE's results.",
keywords = "Capacitance, Delay effects, Delay estimation, Distributed parameter circuits, Equations, Integrated circuit interconnections, Shape, Threshold voltage, Transfer functions, Wire",
author = "Youxin Gao and Wong, {Martin D F}",
year = "2001",
month = "1",
day = "1",
doi = "10.1109/ASPDAC.2001.913363",
language = "English (US)",
series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "533--538",
booktitle = "Proceedings of the ASP-DAC 2001",
address = "United States",

}

TY - GEN

T1 - A fast and accurate delay estimation method for buffered interconnects

AU - Gao, Youxin

AU - Wong, Martin D F

PY - 2001/1/1

Y1 - 2001/1/1

N2 - In this paper, we present a fast and accurate delay estimation method for buffered interconnects. The interconnect wire is modeled by the transmission line model which is more accurate and efficient than lumped circuit model. For the interconnect wire, we specify the wire shape to be of the form f(x)=ae-bx. Note that if we let b=0, our work is reduced to uniform wire case. By using the first three poles in the transfer function, we derive analytical expressions for calculating delay at any threshold voltage under a finite ramp input. The expressions involved in calculating coefficients in the transfer function are also analytical. We use k-factor equations to estimate delays for buffers. Since the k-factor equations require a loading capacitance for delay computation, we use the effective capacitance technique to calculate the effective capacitance for each interconnect wire which is connected to a buffer. Therefore, our delay calculation for buffered interconnects is analytical and thus very efficient. Our experiments show that signal waveforms estimated by our method are very close to SPICE's results.

AB - In this paper, we present a fast and accurate delay estimation method for buffered interconnects. The interconnect wire is modeled by the transmission line model which is more accurate and efficient than lumped circuit model. For the interconnect wire, we specify the wire shape to be of the form f(x)=ae-bx. Note that if we let b=0, our work is reduced to uniform wire case. By using the first three poles in the transfer function, we derive analytical expressions for calculating delay at any threshold voltage under a finite ramp input. The expressions involved in calculating coefficients in the transfer function are also analytical. We use k-factor equations to estimate delays for buffers. Since the k-factor equations require a loading capacitance for delay computation, we use the effective capacitance technique to calculate the effective capacitance for each interconnect wire which is connected to a buffer. Therefore, our delay calculation for buffered interconnects is analytical and thus very efficient. Our experiments show that signal waveforms estimated by our method are very close to SPICE's results.

KW - Capacitance

KW - Delay effects

KW - Delay estimation

KW - Distributed parameter circuits

KW - Equations

KW - Integrated circuit interconnections

KW - Shape

KW - Threshold voltage

KW - Transfer functions

KW - Wire

UR - http://www.scopus.com/inward/record.url?scp=27944464214&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=27944464214&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2001.913363

DO - 10.1109/ASPDAC.2001.913363

M3 - Conference contribution

AN - SCOPUS:27944464214

T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

SP - 533

EP - 538

BT - Proceedings of the ASP-DAC 2001

PB - Institute of Electrical and Electronics Engineers Inc.

ER -