A dual-mode VCO based low-power synthesizer with optimized automatic frequency calibration for software-defined radio

Jin Zhou, Wei Li, Deping Huang, Chen Lian, Ning Li, Junyan Ren

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A low power sigma-delta fractional-N frequency synthesizer for software-defined radio (SDR) implemented in a 0.13m CMOS process is presented, based on a dual-mode VCO (DMVCO) reconfigurable between wideband mode and quadrature mode, with optimized automatic frequency calibration (AFC). The proposed optimized AFC enables a more accurate band selection as well as a lower power for a dual-VCO PLL. A multi-phase counter (MPC) accelerates the calibration process without ruining the calibration accuracy. Simulated phase noise is -123dBc/Hz at 1MHz offset from a 1.8GHz carrier. The spectral purity is better than 45dBc from the output of mixer. The locking time of PLL is about 40s with an AFC time less than 10μs. The 0.4-6GHz synthesizer consumes only 35mW to 51mW from a 1.2V supply.

Original languageEnglish (US)
Title of host publication2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Pages1145-1148
Number of pages4
DOIs
StatePublished - Aug 2 2011
Externally publishedYes
Event2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011 - Rio de Janeiro, Brazil
Duration: May 15 2011May 18 2011

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Other

Other2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
CountryBrazil
CityRio de Janeiro
Period5/15/115/18/11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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