TY - GEN
T1 - A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application
AU - Lee, S.
AU - Chae, J.
AU - Aniya, M.
AU - Takeuchi, S.
AU - Hamashita, K.
AU - Hanumolu, P. K.
AU - Temes, G. C.
PY - 2011
Y1 - 2011
N2 - A cascade switched-capacitor ΔΣ analog-to-digital converter, suitable for WLANs, is presented. It uses a double-sampling scheme with single set of DAC capacitors, and an improved low-distortion architecture with an embedded-adder integrator. The proposed architecture eliminates one active stage, and reduces the output swings in the loop-filter and hence the non-linearity. It was fabricated with a 0.18um CMOS process. The prototype chip achieves 75.5 dB DR, 74 dB SNR, 73.8 dB SNDR, -88.1 dB THD, and 90.2 dB SFDR over a 10 MHz signal band with an FoM of 0.27 pJ/conv-step.
AB - A cascade switched-capacitor ΔΣ analog-to-digital converter, suitable for WLANs, is presented. It uses a double-sampling scheme with single set of DAC capacitors, and an improved low-distortion architecture with an embedded-adder integrator. The proposed architecture eliminates one active stage, and reduces the output swings in the loop-filter and hence the non-linearity. It was fabricated with a 0.18um CMOS process. The prototype chip achieves 75.5 dB DR, 74 dB SNR, 73.8 dB SNDR, -88.1 dB THD, and 90.2 dB SFDR over a 10 MHz signal band with an FoM of 0.27 pJ/conv-step.
UR - http://www.scopus.com/inward/record.url?scp=80455156142&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80455156142&partnerID=8YFLogxK
U2 - 10.1109/CICC.2011.6055289
DO - 10.1109/CICC.2011.6055289
M3 - Conference contribution
AN - SCOPUS:80455156142
SN - 9781457702228
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - 2011 IEEE Custom Integrated Circuits Conference, CICC 2011
T2 - 33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011
Y2 - 19 September 2011 through 21 September 2011
ER -