A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application

S. Lee, J. Chae, M. Aniya, S. Takeuchi, K. Hamashita, P. K. Hanumolu, G. C. Temes

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A cascade switched-capacitor ΔΣ analog-to-digital converter, suitable for WLANs, is presented. It uses a double-sampling scheme with single set of DAC capacitors, and an improved low-distortion architecture with an embedded-adder integrator. The proposed architecture eliminates one active stage, and reduces the output swings in the loop-filter and hence the non-linearity. It was fabricated with a 0.18um CMOS process. The prototype chip achieves 75.5 dB DR, 74 dB SNR, 73.8 dB SNDR, -88.1 dB THD, and 90.2 dB SFDR over a 10 MHz signal band with an FoM of 0.27 pJ/conv-step.

Original languageEnglish (US)
Title of host publication2011 IEEE Custom Integrated Circuits Conference, CICC 2011
DOIs
StatePublished - Nov 9 2011
Externally publishedYes
Event33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011 - San Jose, CA, United States
Duration: Sep 19 2011Sep 21 2011

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011
CountryUnited States
CitySan Jose, CA
Period9/19/119/21/11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application'. Together they form a unique fingerprint.

Cite this