A domain decomposition method for the finite element simulation of circuit board interconnects

Kaiyu Mao, Juin Tan, Jian Ming Jin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A domain decomposition method (DDM) is developed to improve the efficiency of the finite element simulation of interconnects on multilayered printed circuit boards, which helps reduce memory requirements and CPU time without sacrificing the final accuracy. It takes advantage of the multilayered structure and decomposes the board into several single layers separated by power or ground planes. The simulation of each layer can be carried out independently. Connections between neighboring layers are realized by small holes ("vias"), whose computation is accomplished in a trivial final combination procedure. The total memory requirement is only related to the largest single layer. The CPU time is also found to be less than that of the full board simulation. This domain decomposition method further permits a convenient and practical way for parallel computation.

Original languageEnglish (US)
Title of host publicationIEEE 16th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP
Pages279-282
Number of pages4
DOIs
StatePublished - 2007
EventIEEE 16th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP - Atlanta, GA, United States
Duration: Oct 29 2007Oct 31 2007

Publication series

NameIEEE Topical Meeting on Electrical Performance of Electronic Packaging

Other

OtherIEEE 16th Topical Meeting on Electrical Performance of Electronic Packaging, EPEP
Country/TerritoryUnited States
CityAtlanta, GA
Period10/29/0710/31/07

ASJC Scopus subject areas

  • Engineering(all)

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