A distributive-transconductance model for border traps in III-V/high-k MOS capacitors

Chen Zhang, Min Xu, Peide D. Ye, Xiuling Li

Research output: Contribution to journalArticle

Abstract

By in-depth analysis of the electrical response of border traps in gate oxide, a new border-trap model is proposed where the ac charging and discharging current associated with those traps is proportional to the variation of the surface potential of semiconductors, resembling the behavior of transconductors. In contrast, the border trap current is directly related to the local potential in the gate oxide in the existing model. The model is then used to provide a qualitative understanding of the temperature-dependent frequency dispersion observed on the Al2O3/n-GaAs(111)A MOS capacitors at high positive bias.

Original languageEnglish (US)
Article number6513297
Pages (from-to)735-737
Number of pages3
JournalIEEE Electron Device Letters
Volume34
Issue number6
DOIs
StatePublished - Jun 3 2013

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MOS capacitors
Transconductance
Oxides
Surface potential
Semiconductor materials
Temperature

Keywords

  • Border trap
  • III-V
  • MOS

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

A distributive-transconductance model for border traps in III-V/high-k MOS capacitors. / Zhang, Chen; Xu, Min; Ye, Peide D.; Li, Xiuling.

In: IEEE Electron Device Letters, Vol. 34, No. 6, 6513297, 03.06.2013, p. 735-737.

Research output: Contribution to journalArticle

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