A distributed timing analysis framework for large designs

Tsung Wei Huang, Martin D.F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Given ever-increasing circuit complexities, recent trends are driving the requirement for distributed timing analysis (DTA) in electronic design automation (EDA) tools. However, DTA has received little research attention so far and remains a critical problem. In this paper, we introduce a DTA framework for large designs. Our framework supports (1) general design partitions in distributed file systems, (2) non-blocking IO with event-driven loop for effective communication and computation overlap, and (3) an efficient messaging interface between application and network layers. The effectiveness and scalability of our framework has been evaluated on large hierarchical industry designs over a cluster with hundreds of machines.

Original languageEnglish (US)
Title of host publicationProceedings of the 53rd Annual Design Automation Conference, DAC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781450342360
DOIs
StatePublished - Jun 5 2016
Event53rd Annual ACM IEEE Design Automation Conference, DAC 2016 - Austin, United States
Duration: Jun 5 2016Jun 9 2016

Publication series

NameProceedings - Design Automation Conference
Volume05-09-June-2016
ISSN (Print)0738-100X

Other

Other53rd Annual ACM IEEE Design Automation Conference, DAC 2016
CountryUnited States
CityAustin
Period6/5/166/9/16

Fingerprint

Timing Analysis
Distributed File System
Circuit Complexity
Design Automation
Network layers
Event-driven
Scalability
Overlap
Partition
Electronics
Industry
Networks (circuits)
Communication
Requirements
Design
Framework

ASJC Scopus subject areas

  • Computer Science Applications
  • Control and Systems Engineering
  • Electrical and Electronic Engineering
  • Modeling and Simulation

Cite this

Huang, T. W., Wong, M. D. F., Sinha, D., Kalafala, K., & Venkateswaran, N. (2016). A distributed timing analysis framework for large designs. In Proceedings of the 53rd Annual Design Automation Conference, DAC 2016 [a116] (Proceedings - Design Automation Conference; Vol. 05-09-June-2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2897937.2897959

A distributed timing analysis framework for large designs. / Huang, Tsung Wei; Wong, Martin D.F.; Sinha, Debjit; Kalafala, Kerim; Venkateswaran, Natesan.

Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. a116 (Proceedings - Design Automation Conference; Vol. 05-09-June-2016).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Huang, TW, Wong, MDF, Sinha, D, Kalafala, K & Venkateswaran, N 2016, A distributed timing analysis framework for large designs. in Proceedings of the 53rd Annual Design Automation Conference, DAC 2016., a116, Proceedings - Design Automation Conference, vol. 05-09-June-2016, Institute of Electrical and Electronics Engineers Inc., 53rd Annual ACM IEEE Design Automation Conference, DAC 2016, Austin, United States, 6/5/16. https://doi.org/10.1145/2897937.2897959
Huang TW, Wong MDF, Sinha D, Kalafala K, Venkateswaran N. A distributed timing analysis framework for large designs. In Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc. 2016. a116. (Proceedings - Design Automation Conference). https://doi.org/10.1145/2897937.2897959
Huang, Tsung Wei ; Wong, Martin D.F. ; Sinha, Debjit ; Kalafala, Kerim ; Venkateswaran, Natesan. / A distributed timing analysis framework for large designs. Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (Proceedings - Design Automation Conference).
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