A distributed timing analysis framework for large designs

Tsung Wei Huang; Martin D.F. Wong; Debjit Sinha; Kerim Kalafala; Natesan Venkateswaran

doi:10.1145/2897937.2897959

A distributed timing analysis framework for large designs

Tsung Wei Huang, Martin D.F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Given ever-increasing circuit complexities, recent trends are driving the requirement for distributed timing analysis (DTA) in electronic design automation (EDA) tools. However, DTA has received little research attention so far and remains a critical problem. In this paper, we introduce a DTA framework for large designs. Our framework supports (1) general design partitions in distributed file systems, (2) non-blocking IO with event-driven loop for effective communication and computation overlap, and (3) an efficient messaging interface between application and network layers. The effectiveness and scalability of our framework has been evaluated on large hierarchical industry designs over a cluster with hundreds of machines.

Original language	English (US)
Title of host publication	Proceedings of the 53rd Annual Design Automation Conference, DAC 2016
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781450342360
DOIs	https://doi.org/10.1145/2897937.2897959
State	Published - Jun 5 2016
Event	53rd Annual ACM IEEE Design Automation Conference, DAC 2016 - Austin, United States Duration: Jun 5 2016 → Jun 9 2016

Publication series

Name	Proceedings - Design Automation Conference
Volume	05-09-June-2016
ISSN (Print)	0738-100X

Other

Other	53rd Annual ACM IEEE Design Automation Conference, DAC 2016
Country/Territory	United States
City	Austin
Period	6/5/16 → 6/9/16

ASJC Scopus subject areas

Computer Science Applications
Control and Systems Engineering
Electrical and Electronic Engineering
Modeling and Simulation

Online availability

10.1145/2897937.2897959

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Huang, T. W., Wong, M. D. F., Sinha, D., Kalafala, K., & Venkateswaran, N. (2016). A distributed timing analysis framework for large designs. In Proceedings of the 53rd Annual Design Automation Conference, DAC 2016 [a116] (Proceedings - Design Automation Conference; Vol. 05-09-June-2016). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2897937.2897959

A distributed timing analysis framework for large designs. / Huang, Tsung Wei; Wong, Martin D.F.; Sinha, Debjit et al.

Proceedings of the 53rd Annual Design Automation Conference, DAC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. a116 (Proceedings - Design Automation Conference; Vol. 05-09-June-2016).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Huang, TW, Wong, MDF, Sinha, D, Kalafala, K & Venkateswaran, N 2016, A distributed timing analysis framework for large designs. in Proceedings of the 53rd Annual Design Automation Conference, DAC 2016., a116, Proceedings - Design Automation Conference, vol. 05-09-June-2016, Institute of Electrical and Electronics Engineers Inc., 53rd Annual ACM IEEE Design Automation Conference, DAC 2016, Austin, United States, 6/5/16. https://doi.org/10.1145/2897937.2897959

@inproceedings{275ea37bbe194be3b2df018c6261a138,

title = "A distributed timing analysis framework for large designs",

abstract = "Given ever-increasing circuit complexities, recent trends are driving the requirement for distributed timing analysis (DTA) in electronic design automation (EDA) tools. However, DTA has received little research attention so far and remains a critical problem. In this paper, we introduce a DTA framework for large designs. Our framework supports (1) general design partitions in distributed file systems, (2) non-blocking IO with event-driven loop for effective communication and computation overlap, and (3) an efficient messaging interface between application and network layers. The effectiveness and scalability of our framework has been evaluated on large hierarchical industry designs over a cluster with hundreds of machines.",

author = "Huang, {Tsung Wei} and Wong, {Martin D.F.} and Debjit Sinha and Kerim Kalafala and Natesan Venkateswaran",

year = "2016",

month = jun,

day = "5",

doi = "10.1145/2897937.2897959",

language = "English (US)",

series = "Proceedings - Design Automation Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "Proceedings of the 53rd Annual Design Automation Conference, DAC 2016",

address = "United States",

note = "53rd Annual ACM IEEE Design Automation Conference, DAC 2016 ; Conference date: 05-06-2016 Through 09-06-2016",

}

TY - GEN

T1 - A distributed timing analysis framework for large designs

AU - Huang, Tsung Wei

AU - Wong, Martin D.F.

AU - Sinha, Debjit

AU - Kalafala, Kerim

AU - Venkateswaran, Natesan

PY - 2016/6/5

Y1 - 2016/6/5

N2 - Given ever-increasing circuit complexities, recent trends are driving the requirement for distributed timing analysis (DTA) in electronic design automation (EDA) tools. However, DTA has received little research attention so far and remains a critical problem. In this paper, we introduce a DTA framework for large designs. Our framework supports (1) general design partitions in distributed file systems, (2) non-blocking IO with event-driven loop for effective communication and computation overlap, and (3) an efficient messaging interface between application and network layers. The effectiveness and scalability of our framework has been evaluated on large hierarchical industry designs over a cluster with hundreds of machines.

AB - Given ever-increasing circuit complexities, recent trends are driving the requirement for distributed timing analysis (DTA) in electronic design automation (EDA) tools. However, DTA has received little research attention so far and remains a critical problem. In this paper, we introduce a DTA framework for large designs. Our framework supports (1) general design partitions in distributed file systems, (2) non-blocking IO with event-driven loop for effective communication and computation overlap, and (3) an efficient messaging interface between application and network layers. The effectiveness and scalability of our framework has been evaluated on large hierarchical industry designs over a cluster with hundreds of machines.

UR - http://www.scopus.com/inward/record.url?scp=84977143039&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84977143039&partnerID=8YFLogxK

U2 - 10.1145/2897937.2897959

DO - 10.1145/2897937.2897959

M3 - Conference contribution

AN - SCOPUS:84977143039

T3 - Proceedings - Design Automation Conference

BT - Proceedings of the 53rd Annual Design Automation Conference, DAC 2016

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 53rd Annual ACM IEEE Design Automation Conference, DAC 2016

Y2 - 5 June 2016 through 9 June 2016

ER -

A distributed timing analysis framework for large designs

Abstract

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