A digital PLL with a stochastic time-to-digital converter

Volodymyr Kratyuk, Pavan Kumar Hanumolu, Kerem Ok, Kartikeya Mayaram, Un Ku Moon

Research output: Chapter in Book/Report/Conference proceedingConference contribution


A new dual-loop digital PLL (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The test chip has been fabricated in a 0.13μm CMOS process. The DPLL features a 0.7-1.7 GHz oscillator tuning range, 6.9ps rms jitter and consumes 17mW while operating at 1.2GHz.

Original languageEnglish (US)
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Number of pages2
StatePublished - 2006
Externally publishedYes
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: Jun 15 2006Jun 17 2006

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers


Other2006 Symposium on VLSI Circuits, VLSIC
Country/TerritoryUnited States
CityHonolulu, HI

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering


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