TY - GEN
T1 - A digital PLL with a stochastic time-to-digital converter
AU - Kratyuk, Volodymyr
AU - Hanumolu, Pavan Kumar
AU - Ok, Kerem
AU - Mayaram, Kartikeya
AU - Moon, Un Ku
PY - 2006
Y1 - 2006
N2 - A new dual-loop digital PLL (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The test chip has been fabricated in a 0.13μm CMOS process. The DPLL features a 0.7-1.7 GHz oscillator tuning range, 6.9ps rms jitter and consumes 17mW while operating at 1.2GHz.
AB - A new dual-loop digital PLL (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The test chip has been fabricated in a 0.13μm CMOS process. The DPLL features a 0.7-1.7 GHz oscillator tuning range, 6.9ps rms jitter and consumes 17mW while operating at 1.2GHz.
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M3 - Conference contribution
AN - SCOPUS:39549083592
SN - 1424400066
SN - 9781424400065
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 31
EP - 32
BT - 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
T2 - 2006 Symposium on VLSI Circuits, VLSIC
Y2 - 15 June 2006 through 17 June 2006
ER -