A deterministic digital background calibration technique for VCO-based ADCs

Sachin Rao, Karthikeyan Reddy, Brian Young, Pavan Kumar Hanumolu

Research output: Contribution to journalArticle

Abstract

This paper presents a digital background calibration technique to realize a linear voltage-controlled-oscillator (VCO) based ADC. The distortion caused due to the VCO's nonlinear tuning characteristics is eliminated by introducing an inverse voltage-to-frequency transfer function in the signal path. The proposed calibration unit runs in the background and detects the inverse transfer function using a highly digital frequency locked loop. Like many other VCO-based ADCs, the proposed technique does not require analog building blocks such as operational amplifiers, multi-bit feed-back DACs etc., and retains the scaling friendly properties. Implemented in a 90 nm CMOS process, the on-chip calibration improves SNDR of an open-loop VCO-based ADC from 46 dB to more than 73 dB in 5 MHz signal bandwidth while consuming 4.1 mW power. The ADC achieves a figure-of-merit of 91-112 fJ/conv-step for different input frequencies.

Original languageEnglish (US)
Article number6712154
Pages (from-to)950-960
Number of pages11
JournalIEEE Journal of Solid-State Circuits
Volume49
Issue number4
DOIs
StatePublished - Apr 2014

Keywords

  • Background calibration
  • VCO based ADC
  • calibration
  • deterministic calibration
  • open-loop delta sigma
  • time based ADC

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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