A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy

Volodymyr Kratyuk; Pavan Kumar Hanumolu; Un Ku Moon; Kartikeya Mayaram

doi:10.1109/TCSII.2006.889443

A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy

Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un Ku Moon, Kartikeya Mayaram

Research output: Contribution to journal › Article › peer-review

Abstract

In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL.

Original language	English (US)
Pages (from-to)	247-251
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	54
Issue number	3
DOIs	https://doi.org/10.1109/TCSII.2006.889443
State	Published - Mar 7 2007
Externally published	Yes

Keywords

All-digital phase-locked loop (PLL)
bilinear transform
digital loop filter
digitally controlled oscillator

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/TCSII.2006.889443

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abstract = "In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL.",

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A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy

Abstract

Keywords

ASJC Scopus subject areas

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