A design procedure for all-digital phase-locked loops based on a charge-pump phase-locked-loop analogy

Volodymyr Kratyuk, Pavan Kumar Hanumolu, Un Ku Moon, Kartikeya Mayaram

Research output: Contribution to journalArticle

Abstract

In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL.

Original languageEnglish (US)
Pages (from-to)247-251
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume54
Issue number3
DOIs
StatePublished - Mar 7 2007
Externally publishedYes

Keywords

  • All-digital phase-locked loop (PLL)
  • bilinear transform
  • digital loop filter
  • digitally controlled oscillator

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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