TY - GEN
T1 - A deflection criterion for time-interleaved analog-to-digital converters
AU - Bean, Andrew J.
AU - Singer, Andrew Carl
PY - 2011/8/2
Y1 - 2011/8/2
N2 - Analog to digital conversion is often a critical component of a digital communication link. However, the figures of merit that are used in the design of the components that comprise this step are more appropriate for signal reconstruction applications than for digital communication. This paper considers the design of time-interleaved analog-to-digital converters using deflection, or output signal-to-noise ratio, as a tractable design criterion (versus mutual information) for optimizing the phase timing parameters. This criterion is then compared with input to output mutual information, demonstrating their shared qualitative properties. It is shown that for oversampling converters under the deflection criterion, as with mutual information, the optimal sampling phases are not in general equispaced, as is conventionally assumed in converter design.
AB - Analog to digital conversion is often a critical component of a digital communication link. However, the figures of merit that are used in the design of the components that comprise this step are more appropriate for signal reconstruction applications than for digital communication. This paper considers the design of time-interleaved analog-to-digital converters using deflection, or output signal-to-noise ratio, as a tractable design criterion (versus mutual information) for optimizing the phase timing parameters. This criterion is then compared with input to output mutual information, demonstrating their shared qualitative properties. It is shown that for oversampling converters under the deflection criterion, as with mutual information, the optimal sampling phases are not in general equispaced, as is conventionally assumed in converter design.
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U2 - 10.1109/ISCAS.2011.5937552
DO - 10.1109/ISCAS.2011.5937552
M3 - Conference contribution
AN - SCOPUS:79960876373
SN - 9781424494736
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 265
EP - 268
BT - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
T2 - 2011 IEEE International Symposium of Circuits and Systems, ISCAS 2011
Y2 - 15 May 2011 through 18 May 2011
ER -