A critical look at design guidelines for SOI logic gates

Rouwaida Kanj, Elyse Rosenbaum

Research output: Contribution to journal › Article

Abstract

Design guidelines for static and domino SOI CMOS are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-Si. Published design fixes for eliminating parasitic bipolar induced upset are shown to be imperfect. PHI predischarge is thus proposed as an improved method for eliminating data upset due to both bipolar leakage and charge sharing.

Original languageEnglish (US)
JournalProceedings - IEEE International Symposium on Circuits and Systems
Volume3
StatePublished - 2002

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Logic gates

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A critical look at design guidelines for SOI logic gates. / Kanj, Rouwaida; Rosenbaum, Elyse.

In: Proceedings - IEEE International Symposium on Circuits and Systems, Vol. 3, 2002.

Research output: Contribution to journal › Article

Kanj, R & Rosenbaum, E 2002, 'A critical look at design guidelines for SOI logic gates', Proceedings - IEEE International Symposium on Circuits and Systems, vol. 3.
Kanj R, Rosenbaum E. A critical look at design guidelines for SOI logic gates. Proceedings - IEEE International Symposium on Circuits and Systems. 2002;3.
Kanj, Rouwaida ; Rosenbaum, Elyse. / A critical look at design guidelines for SOI logic gates. In: Proceedings - IEEE International Symposium on Circuits and Systems. 2002 ; Vol. 3.
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