A critical look at design guidelines for SOI logic gates

Rouwaida Kanj; Elyse Rosenbaum

A critical look at design guidelines for SOI logic gates

Research output: Contribution to journal › Article

Abstract

Design guidelines for static and domino SOI CMOS are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-Si. Published design fixes for eliminating parasitic bipolar induced upset are shown to be imperfect. PHI predischarge is thus proposed as an improved method for eliminating data upset due to both bipolar leakage and charge sharing.

Original language	English (US)
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
State	Published - 2002

ASJC Scopus subject areas

Electrical and Electronic Engineering

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Kanj, R., & Rosenbaum, E. (2002). A critical look at design guidelines for SOI logic gates. Proceedings - IEEE International Symposium on Circuits and Systems, 3.

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