A critical look at design guidelines for SOI logic gates

Rouwaida Kanj; Elyse Rosenbaum

A critical look at design guidelines for SOI logic gates

Research output: Contribution to journal › Conference article › peer-review

Abstract

Design guidelines for static and domino SOI CMOS are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-Si. Published design fixes for eliminating parasitic bipolar induced upset are shown to be imperfect. PHI predischarge is thus proposed as an improved method for eliminating data upset due to both bipolar leakage and charge sharing.

Original language	English (US)
Pages (from-to)	III/261-III/264
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	3
State	Published - 2002
Event	2002 IEEE International Symposium on Circuits and Systems - Phoenix, AZ, United States Duration: May 26 2002 → May 29 2002

ASJC Scopus subject areas

Electrical and Electronic Engineering

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title = "A critical look at design guidelines for SOI logic gates",

abstract = "Design guidelines for static and domino SOI CMOS are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-Si. Published design fixes for eliminating parasitic bipolar induced upset are shown to be imperfect. PHI predischarge is thus proposed as an improved method for eliminating data upset due to both bipolar leakage and charge sharing.",

author = "Rouwaida Kanj and Elyse Rosenbaum",

year = "2002",

language = "English (US)",

volume = "3",

pages = "III/261--III/264",

journal = "Proceedings - IEEE International Symposium on Circuits and Systems",

issn = "0271-4310",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "2002 IEEE International Symposium on Circuits and Systems ; Conference date: 26-05-2002 Through 29-05-2002",

}

TY - JOUR

T1 - A critical look at design guidelines for SOI logic gates

AU - Kanj, Rouwaida

AU - Rosenbaum, Elyse

PY - 2002

Y1 - 2002

N2 - Design guidelines for static and domino SOI CMOS are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-Si. Published design fixes for eliminating parasitic bipolar induced upset are shown to be imperfect. PHI predischarge is thus proposed as an improved method for eliminating data upset due to both bipolar leakage and charge sharing.

AB - Design guidelines for static and domino SOI CMOS are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-Si. Published design fixes for eliminating parasitic bipolar induced upset are shown to be imperfect. PHI predischarge is thus proposed as an improved method for eliminating data upset due to both bipolar leakage and charge sharing.

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M3 - Conference article

AN - SCOPUS:0036290632

SN - 0271-4310

VL - 3

SP - III/261-III/264

JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2002 IEEE International Symposium on Circuits and Systems

Y2 - 26 May 2002 through 29 May 2002

ER -

A critical look at design guidelines for SOI logic gates

Abstract

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