Design guidelines for static and domino SOI CMOS are evaluated. Restructuring the logic to eliminate gates with large fan-ins is almost as beneficial for SOI as for bulk-Si. Published design fixes for eliminating parasitic bipolar induced upset are shown to be imperfect. PHI predischarge is thus proposed as an improved method for eliminating data upset due to both bipolar leakage and charge sharing.
|Original language||English (US)|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - 2002|
ASJC Scopus subject areas
- Electrical and Electronic Engineering