A continuous-time input pipeline ADC with inherent anti-alias filtering

David Gubbins; Sunwoo Kwon; Bumha Lee; Pavan Kumar Hanumolu; Un Ku Moon

doi:10.1109/CICC.2009.5280858

A continuous-time input pipeline ADC with inherent anti-alias filtering

David Gubbins, Sunwoo Kwon, Bumha Lee, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

The first continuous-time input pipeline Nyquist rate ADC architecture with inherent anti-alias filtering is introduced. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture. Inherent anti-alias filtering is implemented in the first stage MDAC using first order Sinc filtering and a simple RC filter, allowing the possibility of eliminating costly anti-alias filters. The effect of switched-capacitor sampling distortion is reduced. This architecture also eases the jitter requirements of the ADC clock when compared to switched capacitor pipeline ADCs. 9.85 ENOB is achieved with 21.4mW analog power from a 1.8V supply at 26MSPS in a 0.18μm CMOS process.

Original language	English (US)
Title of host publication	2009 IEEE Custom Integrated Circuits Conference, CICC '09
Pages	275-278
Number of pages	4
DOIs	https://doi.org/10.1109/CICC.2009.5280858
State	Published - 2009
Externally published	Yes
Event	2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States Duration: Sep 13 2009 → Sep 16 2009

Other

Other	2009 IEEE Custom Integrated Circuits Conference, CICC '09
Country/Territory	United States
City	San Jose, CA
Period	9/13/09 → 9/16/09

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/CICC.2009.5280858

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title = "A continuous-time input pipeline ADC with inherent anti-alias filtering",

abstract = "The first continuous-time input pipeline Nyquist rate ADC architecture with inherent anti-alias filtering is introduced. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture. Inherent anti-alias filtering is implemented in the first stage MDAC using first order Sinc filtering and a simple RC filter, allowing the possibility of eliminating costly anti-alias filters. The effect of switched-capacitor sampling distortion is reduced. This architecture also eases the jitter requirements of the ADC clock when compared to switched capacitor pipeline ADCs. 9.85 ENOB is achieved with 21.4mW analog power from a 1.8V supply at 26MSPS in a 0.18μm CMOS process.",

author = "David Gubbins and Sunwoo Kwon and Bumha Lee and Hanumolu, {Pavan Kumar} and Moon, {Un Ku}",

year = "2009",

doi = "10.1109/CICC.2009.5280858",

language = "English (US)",

isbn = "9781424440726",

pages = "275--278",

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note = "2009 IEEE Custom Integrated Circuits Conference, CICC '09 ; Conference date: 13-09-2009 Through 16-09-2009",

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AU - Gubbins, David

AU - Kwon, Sunwoo

AU - Lee, Bumha

AU - Hanumolu, Pavan Kumar

AU - Moon, Un Ku

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N2 - The first continuous-time input pipeline Nyquist rate ADC architecture with inherent anti-alias filtering is introduced. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture. Inherent anti-alias filtering is implemented in the first stage MDAC using first order Sinc filtering and a simple RC filter, allowing the possibility of eliminating costly anti-alias filters. The effect of switched-capacitor sampling distortion is reduced. This architecture also eases the jitter requirements of the ADC clock when compared to switched capacitor pipeline ADCs. 9.85 ENOB is achieved with 21.4mW analog power from a 1.8V supply at 26MSPS in a 0.18μm CMOS process.

AB - The first continuous-time input pipeline Nyquist rate ADC architecture with inherent anti-alias filtering is introduced. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture. Inherent anti-alias filtering is implemented in the first stage MDAC using first order Sinc filtering and a simple RC filter, allowing the possibility of eliminating costly anti-alias filters. The effect of switched-capacitor sampling distortion is reduced. This architecture also eases the jitter requirements of the ADC clock when compared to switched capacitor pipeline ADCs. 9.85 ENOB is achieved with 21.4mW analog power from a 1.8V supply at 26MSPS in a 0.18μm CMOS process.

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M3 - Conference contribution

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BT - 2009 IEEE Custom Integrated Circuits Conference, CICC '09

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ER -

A continuous-time input pipeline ADC with inherent anti-alias filtering

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