A new pipeline ADC architecture that employs a continuous-time first stage followed by a conventional switched capacitor pipeline ADC is presented. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture and leads to a low area, low power solution with excellent distortion performance. Measured results obtained from a proof of concept test chip fabricated in a 0.18/μm CMOS process validate the effectiveness of proposed techniques.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - 2008|
ASJC Scopus subject areas
- Electrical and Electronic Engineering