A continuous-time input pipeline ADC

David Gubbins; Bumha Lee; Pavan Kumar Hanumolu; Un Ku Moon

doi:10.1109/CICC.2008.4672050

A continuous-time input pipeline ADC

David Gubbins, Bumha Lee, Pavan Kumar Hanumolu, Un Ku Moon

Research output: Contribution to journal › Conference article › peer-review

Abstract

A new pipeline ADC architecture that employs a continuous-time first stage followed by a conventional switched capacitor pipeline ADC is presented. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture and leads to a low area, low power solution with excellent distortion performance. Measured results obtained from a proof of concept test chip fabricated in a 0.18/μm CMOS process validate the effectiveness of proposed techniques.

Original language	English (US)
Article number	4672050
Pages (from-to)	169-172
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2008.4672050
State	Published - 2008
Externally published	Yes
Event	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States Duration: Sep 21 2008 → Sep 24 2008

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/CICC.2008.4672050

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abstract = "A new pipeline ADC architecture that employs a continuous-time first stage followed by a conventional switched capacitor pipeline ADC is presented. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture and leads to a low area, low power solution with excellent distortion performance. Measured results obtained from a proof of concept test chip fabricated in a 0.18/μm CMOS process validate the effectiveness of proposed techniques.",

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year = "2008",

doi = "10.1109/CICC.2008.4672050",

language = "English (US)",

pages = "169--172",

journal = "Proceedings of the Custom Integrated Circuits Conference",

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AU - Lee, Bumha

AU - Hanumolu, Pavan Kumar

AU - Moon, Un Ku

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N2 - A new pipeline ADC architecture that employs a continuous-time first stage followed by a conventional switched capacitor pipeline ADC is presented. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture and leads to a low area, low power solution with excellent distortion performance. Measured results obtained from a proof of concept test chip fabricated in a 0.18/μm CMOS process validate the effectiveness of proposed techniques.

AB - A new pipeline ADC architecture that employs a continuous-time first stage followed by a conventional switched capacitor pipeline ADC is presented. Such an approach overcomes many of the challenges associated with a pure switched-capacitor architecture and leads to a low area, low power solution with excellent distortion performance. Measured results obtained from a proof of concept test chip fabricated in a 0.18/μm CMOS process validate the effectiveness of proposed techniques.

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ER -

A continuous-time input pipeline ADC

Abstract

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