Using cascode cell, inductance gain boosting and source degeneration techniques in 90 nm CMOS process, a two-stage power amplifier operating at 80 GHz with a minimum chip area of 0.35 mm2 demonstrates gain of 18 dB, linear output power of 10.8 dBm, saturated power of 13.3 dBm, and PAE greater than 11.8% when the amplifier is biased at Vd = 3 V and Vg = 1 V.
- coplanar waveguide (CPW)
- power amplifier (PA)
ASJC Scopus subject areas
- Condensed Matter Physics
- Electrical and Electronic Engineering