A coding framework for low-power address and data busses

Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj

Research output: Contribution to journalArticle

Abstract

This paper presents a source-coding framework for the design of coding schemes to reduce transition activity. These schemes are suited for high-capacitance busses where the extra power dissipation due to the encoder and decoder circuitry is offset by the power savings at the bus. In this framework, a data source (characterized in a probabilistic manner) is first passed through a decorrelating function f1. Next, a variant of entropy coding function f2 is employed, which reduces the transition activity. The framework is then employed to derive novel encoding schemes whereby practical forms for f1 and f2 are proposed. Simulation results with an encoding scheme for data busses indicate an average reduction in transition activity of 36%. This translates into a reduction in total power dissipation for bus capacitances greater than 14 pF/b in 1.2-μm CMOS technology. For a typical value for bus capacitance of 50 pF/b, there is a 36% reduction in power dissipation and eight times more power savings compared to existing schemes. Simulation results with an encoding scheme for instruction address busses indicate an average reduction in transition activity by a factor of 1.5 times over known coding schemes.

Original languageEnglish (US)
Pages (from-to)212-221
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume7
Issue number2
DOIs
StatePublished - Dec 1 1999

Keywords

  • CMOS VLSI
  • Coding
  • High-capacitance busses
  • Low-power design
  • Switching activity

ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering

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