A CMOS design style for logic circuit hardening

Ming Zhang, Naresh R Shanbhag

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

We present a novel CMOS design style that effectively reduces the impact of radiation-induced single event transients (SET) on logic circuits. This design style can be used in both static and dynamic CMOS circuits, and does not require any passive elements such as resistors or capacitors. A static circuit designed in the proposed style will have two output ports while a dynamic circuit will have one. This design style achieves SET mitigation by incorporating two techniques simultaneously: 1) Placing transistors that are closest to the output terminals in isolated wells and tying their body terminals to the corresponding source terminals. The resulting low electric fields across the drain-body and source-body junctions significantly weaken the charge collection efficiency. 2) Attenuating SETs caused by charge collection near other transistors outside the isolated wells via voltage division. Simulations show that in an inverter chain, one inverter stage is sufficient to attenuate the SET generated in the previous stage. This indicates that the soft error rate of a clock distribution network made of hardened inverters is only limited by the last stage, where the local clock signals are applied to sequential logic circuits or the dual outputs are converted to a single output. A hardened D-latch implemented in proposed design style is shown to have a critical charge value of at least 100fC, as compared to the value of 7.5fC for a conventional D-latch. Design examples of complex combinational static and dynamic circuits are also described and simulation results are presented.

Original languageEnglish (US)
Title of host publication2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual
Pages223-229
Number of pages7
StatePublished - Dec 15 2005
Event2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual - San Jose, CA, United States
Duration: Apr 17 2005Apr 21 2005

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Other

Other2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual
CountryUnited States
CitySan Jose, CA
Period4/17/054/21/05

Fingerprint

Logic circuits
Hardening
Networks (circuits)
Transistors
Clock distribution networks
Sequential circuits
Resistors
Clocks
Capacitors
Electric fields
Radiation
Electric potential

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Zhang, M., & Shanbhag, N. R. (2005). A CMOS design style for logic circuit hardening. In 2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual (pp. 223-229). (IEEE International Reliability Physics Symposium Proceedings).

A CMOS design style for logic circuit hardening. / Zhang, Ming; Shanbhag, Naresh R.

2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual. 2005. p. 223-229 (IEEE International Reliability Physics Symposium Proceedings).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zhang, M & Shanbhag, NR 2005, A CMOS design style for logic circuit hardening. in 2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual. IEEE International Reliability Physics Symposium Proceedings, pp. 223-229, 2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual, San Jose, CA, United States, 4/17/05.
Zhang M, Shanbhag NR. A CMOS design style for logic circuit hardening. In 2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual. 2005. p. 223-229. (IEEE International Reliability Physics Symposium Proceedings).
Zhang, Ming ; Shanbhag, Naresh R. / A CMOS design style for logic circuit hardening. 2005 IEEE International Reliability Physics Symposium Proceedings, 43rd Annual. 2005. pp. 223-229 (IEEE International Reliability Physics Symposium Proceedings).
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