Abstract
In this work, we characterize a significant source of software derating that we call instruction-level derating. Instruction-level derating encompasses the mechanisms by which computation on incorrect values can result in correct computation. We characterize the instruction-level derating that occurs in the SPEC CPU2000 INT benchmarks, classifying it (by source) into six categories: value comparison, sub-word operations, logical operations, overflow/precision, lucky loads, and dynamically-dead values. We also characterize the temporal nature of this derating, demonstrating that the effects of a fault persist in architectural state long after the last time they are referenced. Finally, we demonstrate how this characterization can be used to avoid unnecessary error recoveries (when a fault will be masked by software anyway) in the context of a dual modular redundant (DMR) architecture.
Original language | English (US) |
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Pages | 482-491 |
Number of pages | 10 |
DOIs | |
State | Published - 2008 |
Event | 2008 International Conference on Dependable Systems and Networks, DSN-2008 - Anchorage, AK, United States Duration: Jun 24 2008 → Jun 27 2008 |
Other
Other | 2008 International Conference on Dependable Systems and Networks, DSN-2008 |
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Country/Territory | United States |
City | Anchorage, AK |
Period | 6/24/08 → 6/27/08 |
Keywords
- Dual modular redundancy
- Error detection
- Fault injection
- Instruction-level derating
- Software derating
ASJC Scopus subject areas
- Software
- Hardware and Architecture
- Computer Networks and Communications