The problem of routing region definition in the VLSI building-block layout design style is addressed. An algorithm is presented to decompose the routing area into a set of straight channels and switchboxes such that the number of switchboxes in the decomposition is minimized. The algorithm is based on a graph-theoretic approach that makes use of an efficient polynomial time-optimal algorithm for computing minimum clique covers of triangulated graphs. The algorithm was compared with a previously known greedy approach and an exhaustive search optimal algorithm. For all the test problems considered, the new algorithm consistently outperformed the greedy algorithm, and it produced optimal solutions in almost all cases.