A Case for Packageless Processors

Saptadeep Pal, Daniel Petrisko, Adeel A. Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Demand for increasing performance is far outpacing the capability of traditional methods for performance scaling. Disruptive solutions are needed to advance beyond incremental improvements. Traditionally, processors reside inside packages to enable PCB-based integration. We argue that packages reduce the potential memory bandwidth of a processor by at least one order of magnitude, allowable thermal design power (TDP) by up to 70%, and area efficiency by a factor of 5 to 18. Further, silicon chips have scaled well while packages have not. We propose packageless processors - processors where packages have been removed and dies directly mounted on a silicon board using a novel integration technology, Silicon Interconnection Fabric (Si-IF). We show that Si-IF-based packageless processors outperform their packaged counterparts by up to 58% (16% average), 136%(103% average), and 295% (80% average) due to increased memory bandwidth, increased allowable TDP, and reduced area respectively. We also extend the concept of packageless processing to the entire processor and memory system, where the area footprint reduction was up to 76%.

Original languageEnglish (US)
Title of host publicationProceedings - 24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018
PublisherIEEE Computer Society
Pages466-479
Number of pages14
ISBN (Electronic)9781538636596
DOIs
StatePublished - Mar 27 2018
Event24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018 - Vienna, Austria
Duration: Feb 24 2018Feb 28 2018

Publication series

NameProceedings - International Symposium on High-Performance Computer Architecture
Volume2018-February
ISSN (Print)1530-0897

Other

Other24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018
CountryAustria
CityVienna
Period2/24/182/28/18

Keywords

  • Packageless Processors
  • Silicon Interconnect Fabric

ASJC Scopus subject areas

  • Hardware and Architecture

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  • Cite this

    Pal, S., Petrisko, D., Bajwa, A. A., Gupta, P., Iyer, S. S., & Kumar, R. (2018). A Case for Packageless Processors. In Proceedings - 24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018 (pp. 466-479). (Proceedings - International Symposium on High-Performance Computer Architecture; Vol. 2018-February). IEEE Computer Society. https://doi.org/10.1109/HPCA.2018.00047