TY - GEN
T1 - A Case for Packageless Processors
AU - Pal, Saptadeep
AU - Petrisko, Daniel
AU - Bajwa, Adeel A.
AU - Gupta, Puneet
AU - Iyer, Subramanian S.
AU - Kumar, Rakesh
N1 - Funding Information:
X. ACKNOWLEDGEMENT This work was supported in part by the Defense Advanced Research Projects Agency (DARPA) through ONR grant N00014-16-1-263 and the UCLA CHIPS Consortium. The authors would like to thank SivaChandra Jangam for helping with the Si-IF prototype in the paper, and Irina Alam, Matthew Tomei, and the anonymous reviewers for their helpful feedback and suggestions.
Publisher Copyright:
© 2018 IEEE.
PY - 2018/3/27
Y1 - 2018/3/27
N2 - Demand for increasing performance is far outpacing the capability of traditional methods for performance scaling. Disruptive solutions are needed to advance beyond incremental improvements. Traditionally, processors reside inside packages to enable PCB-based integration. We argue that packages reduce the potential memory bandwidth of a processor by at least one order of magnitude, allowable thermal design power (TDP) by up to 70%, and area efficiency by a factor of 5 to 18. Further, silicon chips have scaled well while packages have not. We propose packageless processors - processors where packages have been removed and dies directly mounted on a silicon board using a novel integration technology, Silicon Interconnection Fabric (Si-IF). We show that Si-IF-based packageless processors outperform their packaged counterparts by up to 58% (16% average), 136%(103% average), and 295% (80% average) due to increased memory bandwidth, increased allowable TDP, and reduced area respectively. We also extend the concept of packageless processing to the entire processor and memory system, where the area footprint reduction was up to 76%.
AB - Demand for increasing performance is far outpacing the capability of traditional methods for performance scaling. Disruptive solutions are needed to advance beyond incremental improvements. Traditionally, processors reside inside packages to enable PCB-based integration. We argue that packages reduce the potential memory bandwidth of a processor by at least one order of magnitude, allowable thermal design power (TDP) by up to 70%, and area efficiency by a factor of 5 to 18. Further, silicon chips have scaled well while packages have not. We propose packageless processors - processors where packages have been removed and dies directly mounted on a silicon board using a novel integration technology, Silicon Interconnection Fabric (Si-IF). We show that Si-IF-based packageless processors outperform their packaged counterparts by up to 58% (16% average), 136%(103% average), and 295% (80% average) due to increased memory bandwidth, increased allowable TDP, and reduced area respectively. We also extend the concept of packageless processing to the entire processor and memory system, where the area footprint reduction was up to 76%.
KW - Packageless Processors
KW - Silicon Interconnect Fabric
UR - http://www.scopus.com/inward/record.url?scp=85046745925&partnerID=8YFLogxK
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U2 - 10.1109/HPCA.2018.00047
DO - 10.1109/HPCA.2018.00047
M3 - Conference contribution
AN - SCOPUS:85046745925
T3 - Proceedings - International Symposium on High-Performance Computer Architecture
SP - 466
EP - 479
BT - Proceedings - 24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018
PB - IEEE Computer Society
T2 - 24th IEEE International Symposium on High Performance Computer Architecture, HPCA 2018
Y2 - 24 February 2018 through 28 February 2018
ER -