A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method

Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu

Research output: Contribution to journalArticle

Abstract

A hybrid phase/current-mode phase interpolator (HPC-PI) is presented to improve phase noise performance of ring oscillator based fractional-N PLLs. The proposed HPC-PI alleviates the bandwidth trade-off between VCO phase noise suppression and ΔΣ quantization noise suppression. By combining the phase detection and interpolation functions into XOR phase detector/interpolator (XOR PD-PI) block, accurate quantization error cancellation is achieved without using calibration. Use of a digital MDLL in front of the fractional-N PLL helps in alleviating the bandwidth limitation due to reference frequency and enables bandwidth extension even further. The extended bandwidth helps in suppressing the ring-VCO phase noise and lowering the in-band noise floor. Fabricated in 65 nm CMOS process, the prototype generates fractional frequencies from 4.25 to 4.75 GHz, with in-band phase noise floor of -104 dBc/Hz and 1.5 psrms integrated jitter. The clock multiplier achieves power efficiency of 2.4 mW/GHz and FoM of -225.8 dB.

Original languageEnglish (US)
Article number7029717
Pages (from-to)882-895
Number of pages14
JournalIEEE Journal of Solid-State Circuits
Volume50
Issue number4
DOIs
StatePublished - Apr 1 2015

Fingerprint

Phase locked loops
Phase noise
Interpolation
Calibration
Bandwidth
Variable frequency oscillators
Jitter
Clocks
Detectors

Keywords

  • Calibration-free
  • delta-sigma modulator
  • fractional-N PLL
  • frequency synthesizer
  • multiplying delay-locked loop (MDLL)
  • phase interpolator (PI)
  • phase noise
  • phase-locked loop (PLL)
  • quantization error cancellation
  • ring-VCO

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. / Nandwana, Romesh Kumar; Anand, Tejasvi; Saxena, Saurabh; Kim, Seong Joong; Talegaonkar, Mrunmay; Elkholy, Ahmed; Choi, Woo Seok; Elshazly, Amr; Hanumolu, Pavan Kumar.

In: IEEE Journal of Solid-State Circuits, Vol. 50, No. 4, 7029717, 01.04.2015, p. 882-895.

Research output: Contribution to journalArticle

Nandwana, RK, Anand, T, Saxena, S, Kim, SJ, Talegaonkar, M, Elkholy, A, Choi, WS, Elshazly, A & Hanumolu, PK 2015, 'A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method', IEEE Journal of Solid-State Circuits, vol. 50, no. 4, 7029717, pp. 882-895. https://doi.org/10.1109/JSSC.2014.2385756
Nandwana, Romesh Kumar ; Anand, Tejasvi ; Saxena, Saurabh ; Kim, Seong Joong ; Talegaonkar, Mrunmay ; Elkholy, Ahmed ; Choi, Woo Seok ; Elshazly, Amr ; Hanumolu, Pavan Kumar. / A Calibration-Free Fractional-N Ring PLL Using Hybrid Phase/Current-Mode Phase Interpolation Method. In: IEEE Journal of Solid-State Circuits. 2015 ; Vol. 50, No. 4. pp. 882-895.
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