A bus-oriented multiprocessor architecture specialized for computation of the discrete Fourier transform (DFT) of a length N = 2″ sequential data stream is developed. The architecture distributes computation and memory requirements evenly among the processors and allows flexibility in the number of processors and in the choice of a fast Fourier transform (FFT) algorithm. With three busses, the bus bandwidth equals the input data rate. A single time-multiplexed bus with a bandwidth of three times the input data rate can alternatively be used. The architecture requires processors that have identical hardware, which makes it more attractive than the cascade (pipeline) FFT for multiprocessor implementation.
ASJC Scopus subject areas
- Signal Processing
- Electrical and Electronic Engineering