A Bus-Oriented Multiprocessor Fast Fourier Transform

Douglas L. Jones; Henrik V. Sorensen

doi:10.1109/78.98011

A Bus-Oriented Multiprocessor Fast Fourier Transform

Douglas L. Jones, Henrik V. Sorensen

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

Abstract

A bus-oriented multiprocessor architecture specialized for computation of the discrete Fourier transform (DFT) of a length N = 2″ sequential data stream is developed. The architecture distributes computation and memory requirements evenly among the processors and allows flexibility in the number of processors and in the choice of a fast Fourier transform (FFT) algorithm. With three busses, the bus bandwidth equals the input data rate. A single time-multiplexed bus with a bandwidth of three times the input data rate can alternatively be used. The architecture requires processors that have identical hardware, which makes it more attractive than the cascade (pipeline) FFT for multiprocessor implementation.

Original language	English (US)
Pages (from-to)	2547-2552
Number of pages	6
Journal	IEEE Transactions on Signal Processing
Volume	39
Issue number	11
DOIs	https://doi.org/10.1109/78.98011
State	Published - Nov 1991

ASJC Scopus subject areas

Signal Processing
Electrical and Electronic Engineering

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10.1109/78.98011

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A Bus-Oriented Multiprocessor Fast Fourier Transform

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