This paper describes the design and implementation of a 8×5Gb/s source-synchronous receiver in a 0.13μm CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mimatch in DLLs that reduces the error standard deviations by more than 40% and improves receiver timing margins.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - 2008|
ASJC Scopus subject areas
- Electrical and Electronic Engineering