A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction

Ankur Agrawal, Pavan Kumar Hanumolu, Gu Yeon Wei

Research output: Contribution to journalArticlepeer-review

Abstract

This paper describes the design and implementation of a 8×5Gb/s source-synchronous receiver in a 0.13μm CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mimatch in DLLs that reduces the error standard deviations by more than 40% and improves receiver timing margins.

Original languageEnglish (US)
Article number4672120
Pages (from-to)459-462
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - 2008
Externally publishedYes

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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