This paper describes the design and implementation of a 8×5Gb/s source-synchronous receiver in a 0.13μm CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mimatch in DLLs that reduces the error standard deviations by more than 40% and improves receiver timing margins.
|Number of pages
|Proceedings of the Custom Integrated Circuits Conference
|Published - 2008
|IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States
Duration: Sep 21 2008 → Sep 24 2008
ASJC Scopus subject areas
- Electrical and Electronic Engineering