A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction

Ankur Agrawal; Pavan Kumar Hanumolu; Gu Yeon Wei

doi:10.1109/CICC.2008.4672120

A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction

Ankur Agrawal, Pavan Kumar Hanumolu, Gu Yeon Wei

Research output: Contribution to journal › Article › peer-review

Abstract

This paper describes the design and implementation of a 8×5Gb/s source-synchronous receiver in a 0.13μm CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mimatch in DLLs that reduces the error standard deviations by more than 40% and improves receiver timing margins.

Original language	English (US)
Article number	4672120
Pages (from-to)	459-462
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2008.4672120
State	Published - 2008
Externally published	Yes

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/CICC.2008.4672120

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abstract = "This paper describes the design and implementation of a 8×5Gb/s source-synchronous receiver in a 0.13μm CMOS technology. The receiver employs a cascaded-DLL architecture that avoids filtering of the jitter on the received clock to enhance jitter tolerance bandwidth. A technique is proposed to correct phase spacing mimatch in DLLs that reduces the error standard deviations by more than 40% and improves receiver timing margins.",

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A 8×5 Gb/s source-synchronous receiver with clock generator phase error correction

Abstract

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