TY - GEN
T1 - A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS
AU - Anand, Tejasvi
AU - Talegaonkar, Mrunmay
AU - Elkholy, Ahmed
AU - Saxena, Saurabh
AU - Elshazly, Amr
AU - Hanumolu, Pavan Kumar
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/3/17
Y1 - 2015/3/17
N2 - Energy-proportional operation of serial links is imperative for realizing energy-efficient data centers and low-power mobile interfaces such as MIPI [1]. Burst-mode communication, where the link is powered-off when idle and powered-on when needed, achieves energy proportional operation [2]. Ideally, a burst mode link must be turned on/off in zero time, must consume zero power in the off-state and must incur zero energy overhead while making on/off transitions. However, these requirements are difficult to meet in practice and as a consequence, the efficacy of burst mode communication in achieving energy proportional operation is reduced. The main challenges in achieving small power-on time and off-state power include the design of fast-locking PLLs, CDRs and achieving fast settling of bias node voltages. In this paper, we present a complete 7Gb/s energy-proportional embedded-clock transceiver that achieves less than 20ns power-on time while consuming 63.7mW on-state power, 0.74mW off-state power and 1.2nJ of total transition energy penalty per burst.
AB - Energy-proportional operation of serial links is imperative for realizing energy-efficient data centers and low-power mobile interfaces such as MIPI [1]. Burst-mode communication, where the link is powered-off when idle and powered-on when needed, achieves energy proportional operation [2]. Ideally, a burst mode link must be turned on/off in zero time, must consume zero power in the off-state and must incur zero energy overhead while making on/off transitions. However, these requirements are difficult to meet in practice and as a consequence, the efficacy of burst mode communication in achieving energy proportional operation is reduced. The main challenges in achieving small power-on time and off-state power include the design of fast-locking PLLs, CDRs and achieving fast settling of bias node voltages. In this paper, we present a complete 7Gb/s energy-proportional embedded-clock transceiver that achieves less than 20ns power-on time while consuming 63.7mW on-state power, 0.74mW off-state power and 1.2nJ of total transition energy penalty per burst.
UR - http://www.scopus.com/inward/record.url?scp=84940781100&partnerID=8YFLogxK
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U2 - 10.1109/ISSCC.2015.7062927
DO - 10.1109/ISSCC.2015.7062927
M3 - Conference contribution
AN - SCOPUS:84940781100
T3 - Digest of Technical Papers - IEEE International Solid-State Circuits Conference
SP - 64
EP - 65
BT - 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
Y2 - 22 February 2015 through 26 February 2015
ER -