A 79dB 80MHz 8X-OSR hybrid delta-sigma/pipeline ADC

O. Rajaee, T. Musah, S. Takeuchi, M. Aniya, K. Hamashita, P. Hanumolu, U. Moon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A new delta-sigma modulator architecture is presented. The proposed implementation employs a pipeline ADC as the quantizer of a single-loop delta-sigma modulator and makes use of inherent delays of pipeline ADC stages to enhance overall noise shaping properties. With a 5MHz bandwidth and 80MHz clock, the measured dynamic range and SNDR of this prototype IC are 79dB and 75.4dB. The prototype chip is implemented in a 0.18(im CMOS process.

Original languageEnglish (US)
Title of host publication2009 Symposium on VLSI Circuits
Pages74-75
Number of pages2
StatePublished - Nov 18 2009
Externally publishedYes
Event2009 Symposium on VLSI Circuits - Kyoto, Japan
Duration: Jun 16 2009Jun 18 2009

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Other

Other2009 Symposium on VLSI Circuits
Country/TerritoryJapan
CityKyoto
Period6/16/096/18/09

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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