A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer

Samira Zali Asl; Saurabh Saxena; Pavan Kumar Hanumolu; Kartikeya Mayaram; Terri S. Fiez

doi:10.1109/CICC.2011.6055290

A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer

Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A VCO-based MASH delta-sigma ADC architecture is introduced that uses multi-rating of the two stages. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. To demonstrate this architecture, a prototype consisting of a first-order switched-capacitor (SC) integrator with a 4-bit quantizer operating at 100MHz is followed by a second-stage VCO-based ADC operating at 1.2GHz. The chip is implemented in a 130nm 1P8M CMOS process. The measured SNDR is 77dB for a 4MHz signal bandwidth with a power consumption of 13.8mW from a 1.3V supply. The resulting FoM is 298fJ per conversion.

Original language	English (US)
Title of host publication	2011 IEEE Custom Integrated Circuits Conference, CICC 2011
DOIs	https://doi.org/10.1109/CICC.2011.6055290
State	Published - 2011
Externally published	Yes
Event	33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011 - San Jose, CA, United States Duration: Sep 19 2011 → Sep 21 2011

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
ISSN (Print)	0886-5930

Other

Other	33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011
Country/Territory	United States
City	San Jose, CA
Period	9/19/11 → 9/21/11

ASJC Scopus subject areas

Electrical and Electronic Engineering

Online availability

10.1109/CICC.2011.6055290

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A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. / Asl, Samira Zali; Saxena, Saurabh; Hanumolu, Pavan Kumar et al.
2011 IEEE Custom Integrated Circuits Conference, CICC 2011. 2011. 6055290 (Proceedings of the Custom Integrated Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Asl, SZ, Saxena, S, Hanumolu, PK, Mayaram, K & Fiez, TS 2011, A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. in 2011 IEEE Custom Integrated Circuits Conference, CICC 2011., 6055290, Proceedings of the Custom Integrated Circuits Conference, 33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011, San Jose, CA, United States, 9/19/11. https://doi.org/10.1109/CICC.2011.6055290

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abstract = "A VCO-based MASH delta-sigma ADC architecture is introduced that uses multi-rating of the two stages. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. To demonstrate this architecture, a prototype consisting of a first-order switched-capacitor (SC) integrator with a 4-bit quantizer operating at 100MHz is followed by a second-stage VCO-based ADC operating at 1.2GHz. The chip is implemented in a 130nm 1P8M CMOS process. The measured SNDR is 77dB for a 4MHz signal bandwidth with a power consumption of 13.8mW from a 1.3V supply. The resulting FoM is 298fJ per conversion.",

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AB - A VCO-based MASH delta-sigma ADC architecture is introduced that uses multi-rating of the two stages. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. To demonstrate this architecture, a prototype consisting of a first-order switched-capacitor (SC) integrator with a 4-bit quantizer operating at 100MHz is followed by a second-stage VCO-based ADC operating at 1.2GHz. The chip is implemented in a 130nm 1P8M CMOS process. The measured SNDR is 77dB for a 4MHz signal bandwidth with a power consumption of 13.8mW from a 1.3V supply. The resulting FoM is 298fJ per conversion.

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A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer

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