A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer

Samira Zali Asl, Saurabh Saxena, Pavan Kumar Hanumolu, Kartikeya Mayaram, Terri S. Fiez

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A VCO-based MASH delta-sigma ADC architecture is introduced that uses multi-rating of the two stages. The architecture allows for low power and high speed operation and is insensitive to the VCO linearity. To demonstrate this architecture, a prototype consisting of a first-order switched-capacitor (SC) integrator with a 4-bit quantizer operating at 100MHz is followed by a second-stage VCO-based ADC operating at 1.2GHz. The chip is implemented in a 130nm 1P8M CMOS process. The measured SNDR is 77dB for a 4MHz signal bandwidth with a power consumption of 13.8mW from a 1.3V supply. The resulting FoM is 298fJ per conversion.

Original languageEnglish (US)
Title of host publication2011 IEEE Custom Integrated Circuits Conference, CICC 2011
DOIs
StatePublished - Nov 9 2011
Externally publishedYes
Event33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011 - San Jose, CA, United States
Duration: Sep 19 2011Sep 21 2011

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other33rd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2011
CountryUnited States
CitySan Jose, CA
Period9/19/119/21/11

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Asl, S. Z., Saxena, S., Hanumolu, P. K., Mayaram, K., & Fiez, T. S. (2011). A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer. In 2011 IEEE Custom Integrated Circuits Conference, CICC 2011 [6055290] (Proceedings of the Custom Integrated Circuits Conference). https://doi.org/10.1109/CICC.2011.6055290