TY - GEN
T1 - A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation
AU - Rao, Sachin
AU - Young, Brian
AU - Elshazly, Amr
AU - Yin, Wenjing
AU - Sasidhar, Naga
AU - Hanumolu, Pavan Kumar
PY - 2011
Y1 - 2011
N2 - A highly linear calibration free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning non-linearity of the VCO. The proposed architecture does not require a multi-level feedback DAC and eases anti-aliasing requirements. Fabricated in 90nm CMOS process, the prototype ADC achieves better than 71dB SFDR and 59.1dB SNDR in 8MHz signal bandwidth and consumes 4.3mW.
AB - A highly linear calibration free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning non-linearity of the VCO. The proposed architecture does not require a multi-level feedback DAC and eases anti-aliasing requirements. Fabricated in 90nm CMOS process, the prototype ADC achieves better than 71dB SFDR and 59.1dB SNDR in 8MHz signal bandwidth and consumes 4.3mW.
UR - http://www.scopus.com/inward/record.url?scp=80052662193&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80052662193&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:80052662193
SN - 9784863481657
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 270
EP - 271
BT - 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
T2 - 2011 Symposium on VLSI Circuits, VLSIC 2011
Y2 - 15 June 2011 through 17 June 2011
ER -