Abstract
A highly linear calibration free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning non-linearity of the VCO. The proposed architecture does not require a multi-level feedback DAC and eases anti-aliasing requirements. Fabricated in 90nm CMOS process, the prototype ADC achieves better than 71dB SFDR and 59.1dB SNDR in 8MHz signal bandwidth and consumes 4.3mW.
| Original language | English (US) |
|---|---|
| Title of host publication | 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers |
| Pages | 270-271 |
| Number of pages | 2 |
| State | Published - 2011 |
| Externally published | Yes |
| Event | 2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan Duration: Jun 15 2011 → Jun 17 2011 |
Other
| Other | 2011 Symposium on VLSI Circuits, VLSIC 2011 |
|---|---|
| Country | Japan |
| City | Kyoto |
| Period | 6/15/11 → 6/17/11 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials
Fingerprint Dive into the research topics of 'A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation'. Together they form a unique fingerprint.
Cite this
Rao, S., Young, B., Elshazly, A., Yin, W., Sasidhar, N., & Hanumolu, P. K. (2011). A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation. In 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers (pp. 270-271). [5986448]