Abstract
A highly linear calibration free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning non-linearity of the VCO. The proposed architecture does not require a multi-level feedback DAC and eases anti-aliasing requirements. Fabricated in 90nm CMOS process, the prototype ADC achieves better than 71dB SFDR and 59.1dB SNDR in 8MHz signal bandwidth and consumes 4.3mW.
Original language | English (US) |
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Title of host publication | 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers |
Pages | 270-271 |
Number of pages | 2 |
State | Published - 2011 |
Externally published | Yes |
Event | 2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan Duration: Jun 15 2011 → Jun 17 2011 |
Other
Other | 2011 Symposium on VLSI Circuits, VLSIC 2011 |
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Country | Japan |
City | Kyoto |
Period | 6/15/11 → 6/17/11 |
ASJC Scopus subject areas
- Electrical and Electronic Engineering
- Electronic, Optical and Magnetic Materials