A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation

Sachin Rao; Brian Young; Amr Elshazly; Wenjing Yin; Naga Sasidhar; Pavan Kumar Hanumolu

A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation

Sachin Rao, Brian Young, Amr Elshazly, Wenjing Yin, Naga Sasidhar, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

A highly linear calibration free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning non-linearity of the VCO. The proposed architecture does not require a multi-level feedback DAC and eases anti-aliasing requirements. Fabricated in 90nm CMOS process, the prototype ADC achieves better than 71dB SFDR and 59.1dB SNDR in 8MHz signal bandwidth and consumes 4.3mW.

Original language	English (US)
Title of host publication	2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers
Pages	270-271
Number of pages	2
State	Published - 2011
Externally published	Yes
Event	2011 Symposium on VLSI Circuits, VLSIC 2011 - Kyoto, Japan Duration: Jun 15 2011 → Jun 17 2011

Other

Other	2011 Symposium on VLSI Circuits, VLSIC 2011
Country	Japan
City	Kyoto
Period	6/15/11 → 6/17/11

ASJC Scopus subject areas

Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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Cite this

@inproceedings{e871a7adadaf4623b5ca8300fc42b671,

title = "A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation",

abstract = "A highly linear calibration free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning non-linearity of the VCO. The proposed architecture does not require a multi-level feedback DAC and eases anti-aliasing requirements. Fabricated in 90nm CMOS process, the prototype ADC achieves better than 71dB SFDR and 59.1dB SNDR in 8MHz signal bandwidth and consumes 4.3mW.",

author = "Sachin Rao and Brian Young and Amr Elshazly and Wenjing Yin and Naga Sasidhar and Hanumolu, {Pavan Kumar}",

year = "2011",

language = "English (US)",

isbn = "9784863481657",

pages = "270--271",

booktitle = "2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers",

note = "2011 Symposium on VLSI Circuits, VLSIC 2011 ; Conference date: 15-06-2011 Through 17-06-2011",

}

TY - GEN

T1 - A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation

AU - Rao, Sachin

AU - Young, Brian

AU - Elshazly, Amr

AU - Yin, Wenjing

AU - Sasidhar, Naga

AU - Hanumolu, Pavan Kumar

PY - 2011

Y1 - 2011

N2 - A highly linear calibration free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning non-linearity of the VCO. The proposed architecture does not require a multi-level feedback DAC and eases anti-aliasing requirements. Fabricated in 90nm CMOS process, the prototype ADC achieves better than 71dB SFDR and 59.1dB SNDR in 8MHz signal bandwidth and consumes 4.3mW.

AB - A highly linear calibration free VCO-based ADC uses a two-level modulator to eliminate distortion caused by tuning non-linearity of the VCO. The proposed architecture does not require a multi-level feedback DAC and eases anti-aliasing requirements. Fabricated in 90nm CMOS process, the prototype ADC achieves better than 71dB SFDR and 59.1dB SNDR in 8MHz signal bandwidth and consumes 4.3mW.

UR - http://www.scopus.com/inward/record.url?scp=80052662193&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052662193&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:80052662193

SN - 9784863481657

SP - 270

EP - 271

BT - 2011 Symposium on VLSI Circuits, VLSIC 2011 - Digest of Technical Papers

T2 - 2011 Symposium on VLSI Circuits, VLSIC 2011

Y2 - 15 June 2011 through 17 June 2011

ER -