A 6.8–14-GHz Ring-Based Sampling-PLL Achieving 69.3-fs Jitter Under 50-mV Supply Noise

This article presents a type-III wide-bandwidth ring-oscillator-based analog phase-locked loop (PLL) optimized for low-jitter performance in noisy supply environments. The design uses an 812.5-MHz reference frequency and a high-gain sampling phase detector to achieve a closed-loop bandwidth over 100 MHz, effectively reducing the intrinsic phase noise of the ring oscillator. To improve the voltage-controlled ring oscillator (VCRO) tuning range and supply noise rejection, the PLL includes an additional integrator and an NMOS-based voltage regulator. Fabricated in a 22-nm FinFET process, the proposed integer-N PLL achieves a 13-GHz output with an integrated (10 kHz–100 MHz) jitter of 69.3 fs and supports a continuous tuning range from 6.8 to 14 GHz with an eight-phase output. The supply regulation scheme enhances noise immunity by 31.4 dB, keeping worst case spurious tones below −54 dBc under a 50-mV_pp sinusoidal supply ripple, with minimal jitter degradation (69.3 versus 67.5 fs). The combination of a wide tuning range, low jitter, and strong supply noise suppression makes the proposed PLL ideal for high-speed clock generation in serial links over 100 Gb/s.