A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS

Ahmed Elkholy, Ahmed Elmallah, Mohamed Elzeftawi, Ken Chang, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Injection-locked clock multipliers (ILCMs) achieve superior phase noise compared to conventional PLLs [1, 2]. In its simplest form, an ILCM is an oscillator into which a train of narrow pulses is injected at reference frequency FREF as shown in Fig. 10.6.1. If the free-running frequency, FFR, of the oscillator is tuned close to NFREF (N=4, in Fig. 10.6.1), injected pulses phase lock the oscillator and greatly suppress its close-in phase noise. However, any deviation of FFR from NFREF degrades spurious/jitter performance, making ILCM performance sensitive to PVT variations. A frequency-tracking loop (FTL) was used to continuously tune FFR to be close to NFREF and achieve excellent jitter performance (4psrms) due to mismatch between delay stages. In this work, we seek to overcome this fundamental limitation of conventional ILCMs and extend their benefits to fractional-N ILCMs.

Original languageEnglish (US)
Title of host publication2016 IEEE International Solid-State Circuits Conference, ISSCC 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages192-193
Number of pages2
ISBN (Electronic)9781467394666
DOIs
StatePublished - Feb 23 2016
Event63rd IEEE International Solid-State Circuits Conference, ISSCC 2016 - San Francisco, United States
Duration: Jan 31 2016Feb 4 2016

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume59
ISSN (Print)0193-6530

Other

Other63rd IEEE International Solid-State Circuits Conference, ISSCC 2016
CountryUnited States
CitySan Francisco
Period1/31/162/4/16

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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    Elkholy, A., Elmallah, A., Elzeftawi, M., Chang, K., & Hanumolu, P. K. (2016). A 6.75-to-8.25GHz, 250fsrms-integrated-jitter 3.25mW rapid on/off PVT-insensitive fractional-N injection-locked clock multiplier in 65nm CMOS. In 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016 (pp. 192-193). [7417972] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 59). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2016.7417972