A 6.75-to-8.25GHz 2.25mW 190fs_rms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS

Sub-harmonically injection locked oscillators provide a simple means for generating very-low-noise high-frequency clocks in a power, and area efficient manner [1-5]. Ideally, a free-running oscillator can be locked to the N^th harmonic of a reference clock simply by injecting narrow pulses at reference frequency (F_REF) into the oscillator, such that F_OUT=NF_REF. In the locked state, the oscillator tracks the reference clock and its close-in phase noise is greatly suppressed. As such, the phase noise of an injection-locked clock multiplier (ILCM) is limited only by the noise of reference clock. However, in practice, there are several design challenges that limit usage of ILCMs. First, lock-in range (ΔF_L) of the injection-locked oscillator is limited. Therefore, separate frequency tuning, typically performed using a phase-locked loop (PLL) is needed to bring the oscillator free-running frequency (F_FR) to be within the lock-in range, i.e., F_ERR= F_FR-NF_ref<ΔF_L[5]. If F_ERR≠0 (but <ΔF_L), injection ensures phase locking but causes a reference spur whose magnitude is proportional to F_ERR [1]. The second major challenge is the voltage and temperature (VT) sensitivity of ILCM. F_ERR increases as F_FR drifts due to VT variations, which degrades phase noise and spurious performance and may even lead to loss of lock once F_ERR exceeds ΔF_L [4]. This is especially problematic in the case of high-Q LC oscillators because of their relatively small ΔF_L. Techniques to extend ΔF_L by reducing N or lowering Q are undesirable as smaller N mandates higher F_REF and lower Q incurs a large power penalty.