Sub-harmonically injection locked oscillators provide a simple means for generating very-low-noise high-frequency clocks in a power, and area efficient manner [1-5]. Ideally, a free-running oscillator can be locked to the Nth harmonic of a reference clock simply by injecting narrow pulses at reference frequency (FREF) into the oscillator, such that FOUT=NFREF. In the locked state, the oscillator tracks the reference clock and its close-in phase noise is greatly suppressed. As such, the phase noise of an injection-locked clock multiplier (ILCM) is limited only by the noise of reference clock. However, in practice, there are several design challenges that limit usage of ILCMs. First, lock-in range (ΔFL) of the injection-locked oscillator is limited. Therefore, separate frequency tuning, typically performed using a phase-locked loop (PLL) is needed to bring the oscillator free-running frequency (FFR) to be within the lock-in range, i.e., FERR= FFR-NFref<ΔFL. If FERR≠0 (but <ΔFL), injection ensures phase locking but causes a reference spur whose magnitude is proportional to FERR . The second major challenge is the voltage and temperature (VT) sensitivity of ILCM. FERR increases as FFR drifts due to VT variations, which degrades phase noise and spurious performance and may even lead to loss of lock once FERR exceeds ΔFL . This is especially problematic in the case of high-Q LC oscillators because of their relatively small ΔFL. Techniques to extend ΔFL by reducing N or lowering Q are undesirable as smaller N mandates higher FREF and lower Q incurs a large power penalty.