A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS

Ahmed Elkholy, Mrunmay Talegaonkar, Tejasvi Anand, Pavan Kumar Hanumolu

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Sub-harmonically injection locked oscillators provide a simple means for generating very-low-noise high-frequency clocks in a power, and area efficient manner [1-5]. Ideally, a free-running oscillator can be locked to the Nth harmonic of a reference clock simply by injecting narrow pulses at reference frequency (FREF) into the oscillator, such that FOUT=NFREF. In the locked state, the oscillator tracks the reference clock and its close-in phase noise is greatly suppressed. As such, the phase noise of an injection-locked clock multiplier (ILCM) is limited only by the noise of reference clock. However, in practice, there are several design challenges that limit usage of ILCMs. First, lock-in range (ΔFL) of the injection-locked oscillator is limited. Therefore, separate frequency tuning, typically performed using a phase-locked loop (PLL) is needed to bring the oscillator free-running frequency (FFR) to be within the lock-in range, i.e., FERR= FFR-NFref<ΔFL[5]. If FERR≠0 (but <ΔFL), injection ensures phase locking but causes a reference spur whose magnitude is proportional to FERR [1]. The second major challenge is the voltage and temperature (VT) sensitivity of ILCM. FERR increases as FFR drifts due to VT variations, which degrades phase noise and spurious performance and may even lead to loss of lock once FERR exceeds ΔFL [4]. This is especially problematic in the case of high-Q LC oscillators because of their relatively small ΔFL. Techniques to extend ΔFL by reducing N or lowering Q are undesirable as smaller N mandates higher FREF and lower Q incurs a large power penalty.

Original languageEnglish (US)
Title of host publication2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages188-189
Number of pages2
ISBN (Electronic)9781479962235
DOIs
StatePublished - Mar 17 2015
Event2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers - San Francisco, United States
Duration: Feb 22 2015Feb 26 2015

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
Volume58
ISSN (Print)0193-6530

Other

Other2015 62nd IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers
CountryUnited States
CitySan Francisco
Period2/22/152/26/15

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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  • Cite this

    Elkholy, A., Talegaonkar, M., Anand, T., & Hanumolu, P. K. (2015). A 6.75-to-8.25GHz 2.25mW 190fsrms integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS. In 2015 IEEE International Solid-State Circuits Conference, ISSCC 2015 - Digest of Technical Papers (pp. 188-189). [7062989] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference; Vol. 58). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2015.7062989