TY - JOUR
T1 - A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier
AU - Elkholy, Ahmed
AU - Elmallah, Ahmed
AU - Ahmed, Mostafa Gamal
AU - Hanumolu, Pavan Kumar
N1 - Funding Information:
Manuscript received October 6, 2017; revised December 18, 2017 and February 20, 2018; accepted February 20, 2018. Date of publication March 22, 2018; date of current version May 24, 2018. This paper was approved by Associate Editor Ichiro Fujimori. This work was supported in part by Semiconductor Research Corporation under Grant 1830.125, and in part by Analog Device. (Corresponding author: Ahmed Elkholy.) The authors are with the Department of Electrical and Computer Engineering, University of Illinois at Urbana–Champaign, Urbana, IL 61801 USA (e-mail: elkholy2@illinois.edu).
Publisher Copyright:
© 1966-2012 IEEE.
PY - 2018/6
Y1 - 2018/6
N2 - A rapid ON/OFF LC-based fractional-N injection-locked clock multiplier (ILCM) is presented. The proposed architecture extends the merits of ILCMs to fractional-N operation. It employs a high-resolution digital-to-time converter to align the injected pulses to the oscillator's zero crossings. An all-digital frequency-tracking loop continuously tunes the oscillator free-running frequency toward the target output frequency. The proposed clock multiplier can be powered ON from a completely OFF state almost instantaneously. Background calibration techniques ensure that robust operation across process, voltage, and temperature. Fabricated in 65-nm CMOS process with an active area of 0.27 mm2, the prototype ILCM generates output clock in the range of 6.75-8.25 GHz using a 115-MHz reference clock. It achieves integrated jitter performance of 109 fsrms (integer-N) and 177 fsrms (fractional-N), while consuming only 2.65 (integer-N) and 3.25 mW (fractional-N). This translates to the best-reported FoMJ of -255 (integer-N) and -250 dB (fractional-N). The turn-on time is less than 4 ns in both the integer- and fractional-N modes, illustrating almost instantaneous settling.
AB - A rapid ON/OFF LC-based fractional-N injection-locked clock multiplier (ILCM) is presented. The proposed architecture extends the merits of ILCMs to fractional-N operation. It employs a high-resolution digital-to-time converter to align the injected pulses to the oscillator's zero crossings. An all-digital frequency-tracking loop continuously tunes the oscillator free-running frequency toward the target output frequency. The proposed clock multiplier can be powered ON from a completely OFF state almost instantaneously. Background calibration techniques ensure that robust operation across process, voltage, and temperature. Fabricated in 65-nm CMOS process with an active area of 0.27 mm2, the prototype ILCM generates output clock in the range of 6.75-8.25 GHz using a 115-MHz reference clock. It achieves integrated jitter performance of 109 fsrms (integer-N) and 177 fsrms (fractional-N), while consuming only 2.65 (integer-N) and 3.25 mW (fractional-N). This translates to the best-reported FoMJ of -255 (integer-N) and -250 dB (fractional-N). The turn-on time is less than 4 ns in both the integer- and fractional-N modes, illustrating almost instantaneous settling.
KW - Digital PLL
KW - Phase-locked loop (PLL)
KW - digital-to-time converter (DTC)
KW - digitally controlled oscillator (DCO)
KW - fractional-N
KW - frequency synthesizer
KW - injection-locking
KW - jitter
KW - least-mean square (LMS)
KW - multiplying injection-locked oscillator (MILO)
KW - phase domain response (PDR)
KW - phase noise
KW - sub-harmonic locking
KW - sub-sampling
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U2 - 10.1109/JSSC.2018.2810184
DO - 10.1109/JSSC.2018.2810184
M3 - Article
AN - SCOPUS:85044359653
SN - 0018-9200
VL - 53
SP - 1818
EP - 1829
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 6
ER -