A 6.75-8.25-GHz -250-dB FoM Rapid ON/OFF Fractional-N Injection-Locked Clock Multiplier

Ahmed Elkholy, Ahmed Elmallah, Mostafa Gamal Ahmed, Pavan Kumar Hanumolu

Research output: Contribution to journalArticle

Abstract

A rapid ON/OFF LC-based fractional-N injection-locked clock multiplier (ILCM) is presented. The proposed architecture extends the merits of ILCMs to fractional-N operation. It employs a high-resolution digital-to-time converter to align the injected pulses to the oscillator's zero crossings. An all-digital frequency-tracking loop continuously tunes the oscillator free-running frequency toward the target output frequency. The proposed clock multiplier can be powered ON from a completely OFF state almost instantaneously. Background calibration techniques ensure that robust operation across process, voltage, and temperature. Fabricated in 65-nm CMOS process with an active area of 0.27 mm2, the prototype ILCM generates output clock in the range of 6.75-8.25 GHz using a 115-MHz reference clock. It achieves integrated jitter performance of 109 fsrms (integer-N) and 177 fsrms (fractional-N), while consuming only 2.65 (integer-N) and 3.25 mW (fractional-N). This translates to the best-reported FoMJ of -255 (integer-N) and -250 dB (fractional-N). The turn-on time is less than 4 ns in both the integer- and fractional-N modes, illustrating almost instantaneous settling.

Original languageEnglish (US)
Pages (from-to)1818-1829
Number of pages12
JournalIEEE Journal of Solid-State Circuits
Volume53
Issue number6
DOIs
StatePublished - Jun 2018

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Keywords

  • Digital PLL
  • Phase-locked loop (PLL)
  • digital-to-time converter (DTC)
  • digitally controlled oscillator (DCO)
  • fractional-N
  • frequency synthesizer
  • injection-locking
  • jitter
  • least-mean square (LMS)
  • multiplying injection-locked oscillator (MILO)
  • phase domain response (PDR)
  • phase noise
  • sub-harmonic locking
  • sub-sampling

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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