A 640-Mb/s 2048-bit programmable LDPC decoder chip

Mohammad M. Mansour, Naresh R. Shanbhag

Research output: Contribution to journalArticle

Abstract

A 14.3-mm 2 code-programmable and code-rate tunable decoder chip for 2048-bit low-density parity-check (LDPC) codes is presented. The chip implements the turbo-decoding message-passing (TDMP) algorithm for architecture-aware (AA-)LDPC codes which has a faster convergence rate and hence a throughput advantage over the standard decoding algorithm. It employs a reduced complexity message computation mechanism free of lookup tables, and features a programmable network for message interleaving based on the code structure. The chip decodes any mix of 2048-bit rate-1/2 (3,6)-regular AA-LDPC codes in standard mode by programming the network, and attains a throughput of 640 Mb/s at 125 MHz for 10 TDMP-decoding iterations. In augmented mode, the code rate can be tuned up to 14/16 in steps of 1/16 by augmenting the code. The chip is fabricated in 0.18-μm six-metal-layer CMOS technology, operates at a peak clock frequency of 125 MHz at 1.8 V (nominal), and dissipates an average power of 787 mW.

Original languageEnglish (US)
Pages (from-to)684-697
Number of pages14
JournalIEEE Journal of Solid-State Circuits
Volume41
Issue number3
DOIs
StatePublished - Mar 1 2006

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Keywords

  • Architecture-aware low-density parity-check (AA-LDPC) codes
  • Iterative decoders
  • LDPC codes
  • Turbodecoding message-passing (TDMP) algorithm
  • VLSI decoder architectures

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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