@inproceedings{9e3bb00fddf2451aa3e4c9dbbf09776e,
title = "A 63 dB 16 mW 20 MHz BW double-sampled ΔΣ analog-to-digital converter with an embedded-adder quantizer",
abstract = "A wideband ΔΣ ADC using a novel double-sampling scheme with a single set of capacitors and a dynamic embedded-adder quantizer is presented. The proposed quantizer eliminates static currents in the adder of a low-distortion architecture. Fabricated in 0.18 μm CMOS process, the prototype chip operates with a 320 MHz sampling frequency and achieves 63 dB SNDR in a 20 MHz signal band while consuming 16 mW power.",
author = "J. Chae and S. Lee and M. Aniya and S. Takeuchi and K. Hamashita and Hanumolu, {P. K.} and Temes, {G. C.}",
year = "2010",
doi = "10.1109/CICC.2010.5617594",
language = "English (US)",
isbn = "9781424457588",
series = "Proceedings of the Custom Integrated Circuits Conference",
booktitle = "IEEE Custom Integrated Circuits Conference 2010, CICC 2010",
note = "32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 ; Conference date: 19-09-2010 Through 22-09-2010",
}