A 63 dB 16 mW 20 MHz BW double-sampled ΔΣ analog-to-digital converter with an embedded-adder quantizer

J. Chae, S. Lee, M. Aniya, S. Takeuchi, K. Hamashita, Pavan Kumar Hanumolu, G. C. Temes

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A wideband ΔΣ ADC using a novel double-sampling scheme with a single set of capacitors and a dynamic embedded-adder quantizer is presented. The proposed quantizer eliminates static currents in the adder of a low-distortion architecture. Fabricated in 0.18 μm CMOS process, the prototype chip operates with a 320 MHz sampling frequency and achieves 63 dB SNDR in a 20 MHz signal band while consuming 16 mW power.

Original languageEnglish (US)
Title of host publicationIEEE Custom Integrated Circuits Conference 2010, CICC 2010
DOIs
StatePublished - Dec 13 2010
Externally publishedYes
Event32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010 - San Jose, CA, United States
Duration: Sep 19 2010Sep 22 2010

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other32nd Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2010
CountryUnited States
CitySan Jose, CA
Period9/19/109/22/10

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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